[RFC PATCH 19/22] drm/i915/psr: Remove frontbuffer bit track keeping from PSR
Jouni Högander
jouni.hogander at intel.com
Mon Mar 27 12:37:29 UTC 2023
We are following new strategy to rely purely on dirtyfb callback. PSR
was using frontbuffer bits to keep track of updates between invalidates
and flush. Now as we have only flush we can remove frontbuffer bits
track keeping from PSR as well.
Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 -
.../gpu/drm/i915/display/intel_frontbuffer.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 29 ++-----------------
drivers/gpu/drm/i915/display/intel_psr.h | 3 +-
4 files changed, 5 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0f30942e6931..05e362d7cd24 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1615,7 +1615,6 @@ struct intel_psr {
enum transcoder transcoder;
bool active;
struct work_struct work;
- unsigned int busy_frontbuffer_bits;
bool sink_psr2_support;
bool link_standby;
bool colorimetry_support;
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 3bd48504c678..36b867b938a4 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -85,7 +85,7 @@ void frontbuffer_flush(struct drm_i915_private *i915,
might_sleep();
intel_drrs_flush(i915, frontbuffer_bits);
- intel_psr_flush(i915, frontbuffer_bits);
+ intel_psr_flush(i915);
intel_fbc_flush(i915, frontbuffer_bits);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 6dc51e36cacc..4024d7ee35dd 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -32,7 +32,6 @@
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_aux.h"
-#include "intel_frontbuffer.h"
#include "intel_hdmi.h"
#include "intel_psr.h"
#include "intel_snps_phy.h"
@@ -1256,7 +1255,6 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
- intel_dp->psr.busy_frontbuffer_bits = 0;
intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
/* DC5/DC6 requires at least 6 idle frames */
@@ -2173,20 +2171,12 @@ static void intel_psr_work(struct work_struct *work)
* accordingly in future.
*/
static void
-tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits)
+tgl_dc3co_flush_locked(struct intel_dp *intel_dp)
{
if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled ||
!intel_dp->psr.active)
return;
- /*
- * At every frontbuffer flush flip event modified delay of delayed work,
- * when delayed work schedules that means display has been idle.
- */
- if (!(frontbuffer_bits &
- INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
- return;
-
tgl_psr2_enable_dc3co(intel_dp);
mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work,
intel_dp->psr.dc3co_exit_delay);
@@ -2195,22 +2185,18 @@ tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits)
/**
* intel_psr_flush - Flush PSR
* @dev_priv: i915 device
- * @frontbuffer_bits: frontbuffer plane tracking bits
*
* Since the hardware frontbuffer tracking has gaps we need to integrate
* with the software frontbuffer tracking. This function gets called every
* time frontbuffer rendering has completed and flushed out to memory. PSR
* can be enabled again if no other frontbuffer relevant to PSR is dirty.
*
- * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
*/
-void intel_psr_flush(struct drm_i915_private *dev_priv,
- unsigned int frontbuffer_bits)
+void intel_psr_flush(struct drm_i915_private *dev_priv)
{
struct intel_encoder *encoder;
for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
- unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
mutex_lock(&intel_dp->psr.lock);
@@ -2219,10 +2205,6 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
continue;
}
- pipe_frontbuffer_bits &=
- INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
- intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
-
/*
* If the PSR is paused by an explicit intel_psr_paused() call,
* we have to ensure that the PSR is not activated until
@@ -2232,13 +2214,10 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
goto unlock;
if (!intel_dp->psr.psr2_sel_fetch_enabled) {
- tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits);
+ tgl_dc3co_flush_locked(intel_dp);
goto unlock;
}
- if (pipe_frontbuffer_bits == 0)
- goto unlock;
-
psr_force_hw_tracking_exit(intel_dp);
if (intel_dp->psr.psr2_sel_fetch_enabled)
@@ -2574,8 +2553,6 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
str_enabled_disabled(enabled), val);
psr_source_status(intel_dp, m);
- seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
- psr->busy_frontbuffer_bits);
/*
* SKL+ Perf counter is reset to 0 everytime DC state is entered
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 9d3bf5834444..7f252e8345f2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -27,8 +27,7 @@ void intel_psr_post_plane_update(const struct intel_atomic_state *state);
void intel_psr_disable(struct intel_dp *intel_dp,
const struct intel_crtc_state *old_crtc_state);
int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);
-void intel_psr_flush(struct drm_i915_private *dev_priv,
- unsigned int frontbuffer_bits);
+void intel_psr_flush(struct drm_i915_private *dev_priv);
void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
--
2.34.1
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