[PATCH 1/2] drm/i915: push forcewake writes using readl

[Andrzej Hajda]

On RPL and MTL forcewake sometimes timeouts. Performing read just after
write to fwake register ensures the value is sent to the GPU. If this
help in case of Linux driver similar solution can be applied to GuC,
which also uses fwake and has similar timeout issues.

Signed-off-by: Andrzej Hajda <andrzej.hajda at intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 796ebfe6c55072..bea39253848580 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -120,9 +120,10 @@ intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
 	return "unknown";
 }
 
+#define fw_write(val, reg) ({ writel(val, reg); (void)readl(reg); })
 #define fw_ack(d) readl((d)->reg_ack)
-#define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
-#define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
+#define fw_set(d, val) fw_write(_MASKED_BIT_ENABLE((val)), (d)->reg_set)
+#define fw_clear(d, val) fw_write(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
 
 static inline void
 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
-- 
2.34.1