[PATCH] drm/i915/psr: Adjust time values used for io and fast wake

[Jouni Högander]

We are currently configuring fast wake aux sync count to 24 based on
intel_dp_aux.c:skl_get_aux_send_ctl. This means 16 pulses for pre-chrg
preamble and 8 pulses for preamble. Iowake/fastwake calculation
documentation was assuming this is configured as 16. I.e. 10 pulses for
pre-chrg and 8 for preamble. Fix io and fast wake calculation to use
proper time value 48.

Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d5b739398612..96ca6eb0898b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -850,12 +850,14 @@ static bool _compute_psr2_wake_times(struct intel_dp *intel_dp,
 	u8 max_wake_lines;
 
 	if (DISPLAY_VER(i915) >= 12) {
-		io_wake_time = 42;
 		/*
-		 * According to Bspec it's 42us, but based on testing
-		 * it is not enough -> use 45 us.
+		 * Pre-chrg Preamble (10-16 us) + Preamble (8 us) + PHY-WAKE (4
+		 * us) + tFW_EXIT_LATENCY (20 us)
+		 * Pre-chrg Preamble == 16 us.
+		 * See intel_dp_aux.c:skl_get_aux_send_ctl
 		 */
-		fast_wake_time = 45;
+		io_wake_time = 48;
+		fast_wake_time = 48;
 		max_wake_lines = 12;
 	} else {
 		io_wake_time = 50;
-- 
2.34.1