[PATCH 3/4] drm/dp_mst: Fix PBN divider calculation for UHBR rates

[Imre Deak]

Signed-off-by: Imre Deak <imre.deak at intel.com>
---
 drivers/gpu/drm/display/drm_dp_mst_topology.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 4d72c9a32026e..3ba9c0676db3e 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3586,8 +3586,10 @@ int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
 		drm_dbg_kms(mgr->dev, "invalid link rate/lane count: (%d / %d)\n",
 			    link_rate, link_lane_count);
 
-	/* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
-	return link_rate * link_lane_count / 54000;
+	/* See DP v2.0 2.6.4.2, 2.7.6.3 VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
+	return DIV64_U64_ROUND_UP(mul_u32_u32(link_rate * link_lane_count,
+					      drm_dp_bw_channel_coding_efficiency(link_rate >= 1000000)),
+				100000000ULL * 8 * 54);
 }
 EXPORT_SYMBOL(drm_dp_get_vc_payload_bw);
 
-- 
2.39.2