[PATCH v2 4/4] drm/i915/dp_mst: Add MTL UHBR BS-BS jitter fix
Imre Deak
imre.deak at intel.com
Thu Nov 9 21:41:01 UTC 2023
Signed-off-by: Imre Deak <imre.deak at intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 ++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 107f7418ddc51..519df30bc67b1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -918,6 +918,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
struct drm_dp_mst_atomic_payload *new_payload =
drm_atomic_get_mst_payload_state(new_mst_state, connector->port);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ enum transcoder trans = old_crtc_state->cpu_transcoder;
bool last_mst_stream;
intel_dp->active_mst_links--;
@@ -942,6 +943,10 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
drm_dp_remove_payload_part2(&intel_dp->mst_mgr, new_mst_state,
old_payload, new_payload);
+ if (DISPLAY_VER(dev_priv) >= 14)
+ intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, trans),
+ SEND_SF_BS_JITTER_FIX | ALIGN_DPT_DPTP_MTP_FIX, 0);
+
intel_ddi_disable_transcoder_func(old_crtc_state);
intel_dsc_disable(old_crtc_state);
@@ -1127,10 +1132,21 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base,
drm_atomic_get_mst_payload_state(mst_state, connector->port));
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 12) {
+ u32 clear = FECSTALL_DIS_DPTSTREAM_DPTTG;
+ u32 set;
+
+ if (pipe_config->fec_enable)
+ set |= FECSTALL_DIS_DPTSTREAM_DPTTG;
+
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ clear |= SEND_SF_BS_JITTER_FIX | ALIGN_DPT_DPTP_MTP_FIX;
+ set |= FEC_DP2_0_BS_BS_JITTER_FIX;
+ }
+
intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, trans),
- FECSTALL_DIS_DPTSTREAM_DPTTG,
- pipe_config->fec_enable ? FECSTALL_DIS_DPTSTREAM_DPTTG : 0);
+ clear, set);
+ }
intel_audio_sdp_split_update(pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 135e8d8dbdf06..709dfa82dc651 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4611,7 +4611,10 @@
#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
+#define FEC_DP2_0_BS_BS_JITTER_FIX REG_BIT(15)
+#define ALIGN_DPT_DPTP_MTP_FIX REG_BIT(14)
#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
+#define SEND_SF_BS_JITTER_FIX REG_BIT(4)
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
--
2.39.2
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