[PATCH 3/3] drm/i915/display: Compute and Enable AS SDP
Mitul Golani
mitulkumar.ajitkumar.golani at intel.com
Tue Nov 28 10:48:37 UTC 2023
Add necessary functions definitions to enable
and compute AS SDP data. The new `intel_dp_compute_as_sdp`
function computes AS SDP values based on the display
configuration, ensuring proper handling of Variable Refresh
Rate (VRR).
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani at intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 38f28c480b38..cf42b70b20c3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3918,6 +3918,9 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
+ if(DISPLAY_VER(dev_priv) > 13)
+ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
+
intel_psr_get_config(encoder, pipe_config);
intel_audio_codec_get_config(encoder, pipe_config);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 1fa9e974eb9c..fc476db5228c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2626,6 +2626,24 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
&crtc_state->infoframes.vsc);
}
+static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
+{
+ struct drm_dp_as_sdp *async = &crtc_state->infoframes.async;
+ struct intel_connector *connector = intel_dp->attached_connector;
+ int vrefresh = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
+ if (intel_vrr_is_in_range(connector, vrefresh))
+ return;
+ crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
+ async->sdp_type = DP_SDP_ADAPTIVE_SYNC;
+ async->length = 0x9;
+ async->vmin = crtc_state->vrr.vmin;
+ async->vmax = crtc_state->vrr.vmax;
+ async->target_rr = 0;
+ async->operation_mode = 0x0;
+}
+
void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state,
@@ -2955,6 +2973,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+ intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
return 0;
@@ -4371,6 +4390,9 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
if (!crtc_state->has_psr)
intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
+ if(DISPLAY_VER(dev_priv) >= 13)
+ intel_write_dp_sdp(encoder, crtc_state, DP_SDP_AS_SDP);
+
intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
}
--
2.25.1
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