[PATCH] drm/i915/mtl: Additional delay on message bus read/write

[Mika Kahola]

CI discovered that we may have read/write failures on
message bus. These are sporadic in nature and small amount
of delay in range of 10us to 20us seem to help to '
read or write message bus with increased reliability.

Signed-off-by: Mika Kahola <mika.kahola at intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 7516abf8dba9..f47ad5ef9212 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -212,6 +212,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
 	 * in a known state
 	 */
 	intel_cx0_bus_reset(i915, port, lane);
+	usleep_range(10, 20);
 
 	return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
 }
@@ -298,6 +299,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
 	 * in a known state
 	 */
 	intel_cx0_bus_reset(i915, port, lane);
+	usleep_range(10, 20);
 
 	return 0;
 }
-- 
2.34.1