[PATCH] drm/i915: Remove unnecessary memory quiescing for aux inval
Nirmoy Das
nirmoy.das at intel.com
Tue Sep 19 18:33:12 UTC 2023
i915 already does memory quiesce before signaling
breadcrumb so remove extra memory quiescing for aux
invalidation which can cause unnecessary side effects.
Signed-off-by: Nirmoy Das <nirmoy.das at intel.com>
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 25 ++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 0143445dba83..5afbfb269eca 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -248,11 +248,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
{
struct intel_engine_cs *engine = rq->engine;
- /*
- * On Aux CCS platforms the invalidation of the Aux
- * table requires quiescing memory traffic beforehand
- */
- if (mode & EMIT_FLUSH || gen12_needs_ccs_aux_inv(engine)) {
+ if (mode & EMIT_FLUSH) {
u32 bit_group_0 = 0;
u32 bit_group_1 = 0;
int err;
@@ -264,13 +260,6 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH;
- /*
- * When required, in MTL and beyond platforms we
- * need to set the CCS_FLUSH bit in the pipe control
- */
- if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
- bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;
-
bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
@@ -824,6 +813,18 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
else if (rq->engine->class == COMPUTE_CLASS)
flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
+ /*
+ * On Aux CCS platforms the invalidation of the Aux
+ * table requires quiescing memory traffic beforehand.
+ * gen12_emit_fini_breadcrumb_rcs() does this for us as
+ * all memory traffic has to be completed before we signal
+ * the breadcrumb. In MTL and beyond platforms, we need to also
+ * add CCS_FLUSH bit in the pipe control for that purpose.
+ */
+
+ if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
+ bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;
+
cs = gen12_emit_pipe_control(cs, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0);
/*XXX: Look at gen8_emit_fini_breadcrumb_rcs */
--
2.41.0
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