[PATCH 0/5] Implement Wa_14021768792 to bypass m_n ratio limit

[Ankit Nautiyal]

As per Bspec:68922 platforms BMG and Display > 14 which support higher
link rates have a HW limitation:
If the CEILING( Link M / Link N ) ratio is greater than 10.0, then
hardware cannot support the given resolution / refresh rate at the given
configuration.

This series implements Wa_14021768792 to bypass this limitation on BMG.

Ankit Nautiyal (5):
  drm/i915/display: Add bits for link_n_exended for DISPLAY >= 14
  drm/i915/display: Limit m/n ratio to 10 for BMG + Display > 14
  drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
  drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n
    ratio > 10
  drm/i915: Add Wa_14021768792 as per WA framework

 drivers/gpu/drm/i915/display/intel_display.c  | 126 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_display.h  |  13 +-
 .../drm/i915/display/intel_display_types.h    |   3 +
 .../gpu/drm/i915/display/intel_display_wa.h   |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  64 +++++++--
 drivers/gpu/drm/i915/display/intel_dp.h       |   4 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  29 ++--
 drivers/gpu/drm/i915/display/intel_fdi.c      |  15 ++-
 drivers/gpu/drm/i915/i915_reg.h               |   7 +
 drivers/gpu/drm/xe/display/xe_display_wa.c    |   5 +
 drivers/gpu/drm/xe/xe_wa_oob.rules            |   1 +
 11 files changed, 227 insertions(+), 42 deletions(-)

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2.45.2