[PATCH 08/11] drm/i915/gt: Store active CCS mask

Andi Shyti andi.shyti at linux.intel.com
Mon Aug 19 17:15:19 UTC 2024


To support upcoming patches, we need to store the current mask
for active CCS engines.

Active engines refer to those exposed to userspace via the UABI
engine list.

Signed-off-by: Andi Shyti <andi.shyti at linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 29 ++++++++++++++++++---
 drivers/gpu/drm/i915/gt/intel_gt_types.h    |  1 +
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
index 895f4805cbe0..66aa2ec82fec 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
@@ -12,10 +12,10 @@
 static void intel_gt_apply_ccs_mode(struct intel_gt *gt)
 {
 	unsigned long cslices_mask = CCS_MASK(gt);
+	u32 m = hweight32(gt->ccs.ccs_mask);
 	u32 mode_val = 0;
 	int ccs_id;
 	int cslice;
-	u32 m = 1;
 
 	lockdep_assert_held(&gt->ccs.mutex);
 
@@ -76,7 +76,8 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt)
 		mode_val |= XEHP_CCS_MODE_CSLICE(cslice, ccs_id);
 
 		if (!m) {
-			m = 1; /* CCS mode, will be used later to reset to a flexible value */
+			/* CCS mode, reset to the initial mode */
+			m = hweight32(gt->ccs.ccs_mask);
 			ccs_id = __ffs(cslices_mask);
 			continue;
 		}
@@ -88,13 +89,33 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt)
 	gt->ccs.mode_reg_val = mode_val;
 }
 
+static void update_ccs_mask(struct intel_gt *gt, u32 ccs_mode)
+{
+	unsigned long cslices_mask = CCS_MASK(gt);
+	int i;
+
+	/* Mask off all the CCS engines */
+	gt->ccs.ccs_mask = 0;
+
+	for_each_set_bit(i, &cslices_mask, I915_MAX_CCS) {
+		gt->ccs.ccs_mask |= BIT(i);
+
+		ccs_mode--;
+		if (!ccs_mode)
+			break;
+	}
+
+	/* Initialize the CCS mode setting */
+	intel_gt_apply_ccs_mode(gt);
+}
+
 void intel_gt_ccs_mode_init(struct intel_gt *gt)
 {
 	mutex_init(&gt->ccs.mutex);
 
-	/* Initialize the CCS mode setting */
+	/* Set CCS balance mode 1 in the ccs_mask */
 	mutex_lock(&gt->ccs.mutex);
-	intel_gt_apply_ccs_mode(gt);
+	update_ccs_mask(gt, 1);
 	mutex_unlock(&gt->ccs.mutex);
 }
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index a833b395237b..235b4b81eecd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -220,6 +220,7 @@ struct intel_gt {
 	struct {
 		struct mutex mutex;
 		u32 mode_reg_val;
+		intel_engine_mask_t ccs_mask;
 	} ccs;
 
 	/*
-- 
2.45.2



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