[PATCH 4/8] drm/i915/psr: Use PSR2_MAN_TRK_CTL start/end to send full update

[Jouni Högander]

We are preparing for a change where only frontbuffer flush will use
single/continuous full frame bits or new registers SFF_CTL and CFF_CTL
available on LunarLake onwards.

Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++----------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2229e07e1fff..941b6c4bb1fe 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2382,31 +2382,32 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 val = man_trk_ctl_enable_bit_get(display);
-
-	/* SF partial frame enable has to be set even on full update */
-	val |= man_trk_ctl_partial_frame_bit_get(display);
+	u32 su_region_start_line, su_region_end_line;
 
 	if (full_update) {
-		val |= man_trk_ctl_single_full_frame_bit_get(display);
-		val |= man_trk_ctl_continuos_full_frame(display);
-		goto exit;
+		su_region_start_line = 0;
+		su_region_end_line = crtc_state->hw.adjusted_mode.crtc_vtotal;
+	} else {
+		val |= man_trk_ctl_partial_frame_bit_get(display);
+		su_region_start_line = crtc_state->psr2_su_area.y1;
+		su_region_end_line = crtc_state->psr2_su_area.y2;
 	}
 
 	if (crtc_state->psr2_su_area.y1 == -1)
 		goto exit;
 
 	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(display) >= 14) {
-		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1);
-		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1);
+		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(su_region_start_line);
+		val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(su_region_end_line - 1);
 	} else {
 		drm_WARN_ON(crtc_state->uapi.crtc->dev,
-			    crtc_state->psr2_su_area.y1 % 4 ||
-			    crtc_state->psr2_su_area.y2 % 4);
+			    su_region_start_line % 4 ||
+			    su_region_end_line % 4);
 
 		val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(
-			crtc_state->psr2_su_area.y1 / 4 + 1);
+			su_region_start_line / 4 + 1);
 		val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(
-			crtc_state->psr2_su_area.y2 / 4 + 1);
+			su_region_end_line / 4 + 1);
 	}
 exit:
 	crtc_state->psr2_man_track_ctl = val;
@@ -2608,6 +2609,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		goto skip_sel_fetch_set_loop;
 	}
 
+	if (1) {
+		full_update = true;
+		goto skip_sel_fetch_set_loop;
+	}
+
 	crtc_state->psr2_su_area.x1 = 0;
 	crtc_state->psr2_su_area.y1 = -1;
 	crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src);
-- 
2.34.1