[PATCH 22/23] drm/i915/vrr: Always use VRR timing generator for XE2LPD+

[Ankit Nautiyal]

Currently VRR timing generator is used only when VRR is enabled by
userspace. From XE2LPD+, gradually move away from older timing
generator and use VRR timing generator for fixed refresh rate also.

In such a case, Flipline Vmin and Vmax all are set to the Vtotal of the
mode, which effectively makes the VRR timing generator work in
fixed refresh rate mode.
The MSA Vtotal is derived from Vmax register.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 77 +++++++++++++++++++++---
 1 file changed, 69 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5f4d835880be..c023cb3f438a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -238,9 +238,26 @@ bool intel_vrrtg_is_enabled(const struct intel_crtc_state *crtc_state)
 	return crtc_state->vrr.mode != INTEL_VRRTG_MODE_NONE;
 }
 
-void
-intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
-			 struct drm_connector_state *conn_state)
+static
+void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
+{
+	/*
+	 * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
+	 * Vtotal value. The sink uses MSA timings for the fixed refresh rate
+	 * mode. The HW prepares the Vtotal for the MSA from the VMAX register.
+	 * Since the MSA Vtotal is one-based while Vmax is zero-based we need to
+	 * take care of this while setting Vmax value.
+	 */
+	crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.vtotal - 1;
+	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
+	crtc_state->vrr.flipline = crtc_state->vrr.vmax;
+	crtc_state->vrr.mode = INTEL_VRRTG_MODE_FIXED_RR;
+	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+}
+
+static
+void intel_vrr_compute_xe2lpd_timings(struct intel_crtc_state *crtc_state,
+				      struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_connector *connector =
@@ -248,13 +265,36 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	bool is_edp = intel_dp_is_edp(intel_dp);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
-	int vmin, vmax;
+	int vmin = 0, vmax = 0;
 
-	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
-		return;
+	if (crtc_state->vrr.in_range) {
+		if (HAS_LRR(display))
+			crtc_state->update_lrr = true;
+
+		vmin = intel_vrr_compute_vmin(connector, adjusted_mode);
+		vmax = intel_vrr_compute_vmax(connector, adjusted_mode);
+	}
+
+	if (vmin < vmax && crtc_state->uapi.vrr_enabled)
+		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
+	else if (vmin < vmax && is_cmrr_frac_required(crtc_state) && is_edp)
+		intel_vrr_compute_cmrr_timings(crtc_state);
+	else
+		intel_vrr_compute_fixed_rr_timings(crtc_state);
+}
+
+static
+void intel_vrr_compute_xelpd_timings(struct intel_crtc_state *crtc_state,
+				     struct drm_connector_state *conn_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_connector *connector =
+		to_intel_connector(conn_state->connector);
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
+	bool is_edp = intel_dp_is_edp(intel_dp);
+	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	int vmin, vmax;
 
-	crtc_state->vrr.in_range =
-		intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode));
 	if (!crtc_state->vrr.in_range)
 		return;
 
@@ -273,6 +313,27 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 		intel_vrr_compute_cmrr_timings(crtc_state);
 	else
 		intel_vrr_prepare_vrr_timings(crtc_state, vmin, vmax);
+}
+
+void
+intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
+			 struct drm_connector_state *conn_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_connector *connector =
+		to_intel_connector(conn_state->connector);
+	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+		return;
+
+	crtc_state->vrr.in_range =
+		intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode));
+
+	if (DISPLAY_VER(display) >= 20)
+		intel_vrr_compute_xe2lpd_timings(crtc_state, conn_state);
+	else
+		intel_vrr_compute_xelpd_timings(crtc_state, conn_state);
 
 	if (HAS_AS_SDP(display)) {
 		crtc_state->vrr.vsync_start =
-- 
2.45.2