[PATCH 2/2] drm/i915/display/dp: 128/132b DP-capable with SST

[Arun R Murthy]

With a value of '0' read from MSTM_CAP register MST to be enabled.
DP2.1 SCR updates the spec for 128/132b DP capable supporting only one
stream and not supporting single stream sideband MSG.
The underlying protocol will be MST to enable use of MTP.

v2: Replace checking for max link rate with dpcd link capability(Jani N)

Signed-off-by: Arun R Murthy <arun.r.murthy at intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 47 ++++++++++++++++++++-----
 1 file changed, 38 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9ff0cbd9c0df..e23b214eb54c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4010,6 +4010,32 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
 					   intel_dp->downstream_ports) == 0;
 }
 
+static int
+intel_dp_mst_topology_mgr_mst_start(struct drm_i915_private *i915,
+				    struct intel_dp *intel_dp)
+{
+	int ret;
+
+	ret = drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, true);
+	if (ret < 0)
+		drm_err(&i915->drm, "Failed to enable the device into MST mode!");
+
+	return ret;
+}
+
+static int
+intel_dp_mst_topology_mgr_mst_stop(struct drm_i915_private *i915,
+				    struct intel_dp *intel_dp)
+{
+	int ret;
+
+	ret = drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, false);
+	if (ret < 0)
+		drm_err(&i915->drm, "DM_MST: Failed to disable the device MST mode!");
+
+	return ret;
+}
+
 static bool
 intel_dp_can_mst(struct intel_dp *intel_dp)
 {
@@ -4038,11 +4064,16 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
 	if (!intel_dp_mst_source_support(intel_dp))
 		return;
 
-	intel_dp->is_mst = sink_can_mst &&
-		i915->display.params.enable_dp_mst;
-
-	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
-					intel_dp->is_mst);
+	intel_dp->is_mst = sink_can_mst && i915->display.params.enable_dp_mst;
+	/*
+	 * Even if dpcd reg MSTM_CAP is 0, if the sink supports UHBR rates then
+	 * DP2.1 can be enabled with underlying protocol using MST for MTP
+	 * TODO: Need to accomodate MSTM_CAP bit[0]=0, bit[1]=1 condition, i.e
+	 * one stream with single stream sideband msg.
+	 */
+	if (intel_dp->is_mst || (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] &
+				DP_CAP_ANSI_128B132B))
+		intel_dp_mst_topology_mgr_mst_start(i915, intel_dp);
 }
 
 static bool
@@ -5661,8 +5692,7 @@ intel_dp_detect(struct drm_connector *connector,
 				    intel_dp->is_mst,
 				    intel_dp->mst_mgr.mst_state);
 			intel_dp->is_mst = false;
-			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
-							intel_dp->is_mst);
+			intel_dp_mst_topology_mgr_mst_stop(dev_priv, intel_dp);
 		}
 
 		goto out;
@@ -6562,8 +6592,7 @@ void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
 						     true);
 		if (ret) {
 			intel_dp->is_mst = false;
-			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
-							false);
+			intel_dp_mst_topology_mgr_mst_stop(dev_priv, intel_dp);
 		}
 	}
 }
-- 
2.25.1