[PATCH] drm/i915/display: Workaround to force full modeset for MTL+

[Mika Kahola]

For MTL+ platforms the eDP and TC are routed via PICA C10 or C20
chips. Since the PLL settings may differ between the driver sw
state and the ones that GOP programs, the PLL state verification
may yield an error. To rely only on sw pll settings, the workaround
forces full modeset to take place and hence force the driver PLL
settings to be written in hw.

Signed-off-by: Mika Kahola <mika.kahola at intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a755b1f13d51..f5893152f86f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4162,7 +4162,8 @@ static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
 	enum phy phy = intel_port_to_phy(i915, encoder->port);
 	bool fastset = true;
 
-	if (intel_phy_is_tc(i915, phy)) {
+	if (IS_LUNARLAKE(i915) || IS_METEORLAKE(i915) ||
+	    intel_phy_is_tc(i915, phy)) {
 		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",
 			    encoder->base.base.id, encoder->base.name);
 		crtc_state->uapi.mode_changed = true;
-- 
2.34.1