[PATCH] drm/i915/display: Add quirk to disable fastset on eDP panel

[Mika Kahola]

On BOM10 panel there is a mismatch between hw and sw PLL settings.
With fastset the hw is programmed with different PLL value than
sw state defines. Hence, let's disable fastset and let driver
to program sw state to hw with full modeset.

Signed-off-by: Mika Kahola <mika.kahola at intel.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c  | 2 ++
 drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++++
 include/drm/display/drm_dp_helper.h      | 8 ++++++++
 3 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index f5d4be897866..3a60f8d1d1e2 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2283,6 +2283,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
 	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
 	/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
 	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
+	/* BOM10 panel fastset disabled */
+	{ OUI(0x38, 0xec, 0x11), DEVICE_ID(1, 0, 0, 0, 0, 1), false, BIT(DP_DPCD_QUIRK_DISABLE_FASTSET) },
 };
 
 #undef OUI
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a3d3d4942eb1..4d54ce54cd05 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4147,8 +4147,14 @@ static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
 					    struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *dp = enc_to_intel_dp(encoder);
 	bool fastset = true;
 
+	if (drm_dp_has_quirk(&dp->desc, DP_DPCD_QUIRK_DISABLE_FASTSET)) {
+		crtc_state->uapi.mode_changed = true;
+		fastset = false;
+	}
+
 	if (intel_encoder_is_tc(encoder)) {
 		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",
 			    encoder->base.base.id, encoder->base.name);
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 6c6a96496df6..10a9e96edd60 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -671,6 +671,14 @@ enum drm_dp_quirk {
 	 * requires enabling DSC.
 	 */
 	DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
+
+	/**
+	 * @DP_DPCD_QUIRK_DISABLE_FASTSET:
+	 *
+	 * The PLL settings differ between HW and SW so disable fastset
+	 * option
+	 */
+	DP_DPCD_QUIRK_DISABLE_FASTSET,
 };
 
 /**
-- 
2.34.1