[RFC v1] drm/i915/vrr: Trigger DMC fw for DCB

[Mitul Golani]

Trigger related events to DMC in accordabce to trigger DCB.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani at intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c      | 15 ++++++++++
 drivers/gpu/drm/i915/display/intel_vrr_regs.h | 29 +++++++++++++++++++
 2 files changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 19a5d0076bb8..1198f740ab75 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -345,6 +345,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	int val;
 
 	if (!crtc_state->vrr.enable)
 		return;
@@ -365,6 +366,15 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	} else {
 		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
 			       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+		if (DISPLAY_VER(display) >= 30) {
+			intel_de_write(display, PIPEDMC_DCB_CTL(display, cpu_transcoder),
+				       DCB_CTL_ENABLE);
+
+			val = PIPEDMC_EVT_ADAPTIVE_DC_BALANCE_TRIGGER | PIPEDMC_EVT_ENABLE |
+				  PIPEDMC_EVT_RECURRENCE | PIPEDMC_EVT_EDGE_0_1;
+			intel_de_write(display, PIPEDMC_EVT_CTL_2(display, cpu_transcoder),
+				       val);
+		}
 	}
 }
 
@@ -378,6 +388,11 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
 		       trans_vrr_ctl(old_crtc_state));
+	if (DISPLAY_VER(display) >= 30) {
+		intel_de_write(display, PIPEDMC_DCB_CTL(display, cpu_transcoder), 0);
+		intel_de_write(display, PIPEDMC_EVT_CTL_2(display, cpu_transcoder), 0);
+	}
+
 	intel_de_wait_for_clear(display,
 				TRANS_VRR_STATUS(display, cpu_transcoder),
 				VRR_STATUS_VRR_EN_LIVE, 1000);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 6ed0e0dc97e7..d30a27843c12 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -8,6 +8,35 @@
 
 #include "intel_display_reg_defs.h"
 
+#define _PIPEDMC_EVT_CTL_2_A					0x5F03C
+#define _PIPEDMC_EVT_CTL_2_B					0x5F43C
+#define _PIPEDMC_EVT_CTL_2_C					0x5F83C
+#define _PIPEDMC_EVT_CTL_2_D					0x5FC3C
+#define _PIPEDMC_EVT_CTL_2_E					0x5503C
+#define _PIPEDMC_EVT_CTL_2_F					0x5543C
+#define PIPEDMC_EVT_CTL_2(dev_priv, trans)			_MMIO_TRANS2(dev_priv,\
+									     trans,\
+									     _PIPEDMC_EVT_CTL_2_A)
+#define PIPEDMC_EVT_ENABLE					REG_BIT(31)
+#define PIPEDMC_EVT_RECURRENCE					REG_BIT(30)
+#define PIPEDMC_EVT_ADAPTIVE_DC_BALANCE_TRIGGER 0x3D
+
+enum event_type {
+	PIPEDMC_EVT_LEVEL_0 = 0,
+	PIPEDMC_EVT_LEVEL_1,
+	PIPEDMC_EVT_EDGE_1_0,
+	PIPEDMC_EVT_EDGE_0_1,
+};
+
+#define _PIPEDMC_DCB_CTL_A			0x5F1A0
+#define _PIPEDMC_DCB_CTL_B			0x5F5A0
+#define _PIPEDMC_DCB_CTL_C			0x5F9A0
+#define _PIPEDMC_DCB_CTL_D			0x5FDA0
+#define _PIPEDMC_DCB_CTL_E			0x551A0
+#define _PIPEDMC_DCB_CTL_F			0x555A0
+#define PIPEDMC_DCB_CTL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_CTL_A)
+#define DCB_CTL_ENABLE				REG_BIT(31)
+
 /* VRR registers */
 #define _TRANS_VRR_CTL_A			0x60420
 #define _TRANS_VRR_CTL_B			0x61420
-- 
2.46.0