[PATCH 22/23] drm/i915/vrr: Always use VRR timing generator for XE2LPD+
Ankit Nautiyal
ankit.k.nautiyal at intel.com
Thu Nov 7 10:29:11 UTC 2024
Currently VRR timing generator is used only when VRR is enabled by
userspace. From XE2LPD+, gradually move away from older timing
generator and use VRR timing generator for fixed refresh rate also.
In such a case, Flipline VMin and VMax all are set to the Vtotal of the
mode, which effectively makes the VRR timing generator work in
fixed refresh rate mode
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 68 ++++++++++++++++++------
1 file changed, 52 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 25fb63ca3ef2..4b8343424b6c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -235,6 +235,41 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state, int vmin
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
+static
+void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
+{
+ crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.vtotal - 1;
+ crtc_state->vrr.vmin = crtc_state->vrr.vmax;
+ crtc_state->vrr.flipline = crtc_state->vrr.vmax;
+ crtc_state->vrr.tg_enable = true;
+ crtc_state->vrr.mode = INTEL_VRRTG_MODE_FIXED_RR;
+ crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+}
+
+static
+void intel_vrr_compute_xe2lpd_timings(struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct intel_connector *connector =
+ to_intel_connector(conn_state->connector);
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
+ bool is_edp = intel_dp_is_edp(intel_dp);
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ int vmin = 0, vmax = 0;
+
+ if (crtc_state->vrr.in_range) {
+ vmin = intel_vrr_compute_vmin(connector, adjusted_mode);
+ vmax = intel_vrr_compute_vmax(connector, adjusted_mode);
+ }
+
+ if (crtc_state->vrr.in_range && vmin < vmax && crtc_state->uapi.vrr_enabled)
+ intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
+ else if (crtc_state->vrr.in_range && vmin < vmax && is_cmrr_frac_required(crtc_state) && is_edp)
+ intel_vrr_compute_cmrr_timings(crtc_state);
+ else
+ intel_vrr_compute_fixed_rr_timings(crtc_state);
+}
+
void
intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
@@ -245,31 +280,32 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct intel_dp *intel_dp = intel_attached_dp(connector);
bool is_edp = intel_dp_is_edp(intel_dp);
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
- int vmin, vmax;
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
return;
crtc_state->vrr.in_range =
intel_vrr_is_in_range(connector, drm_mode_vrefresh(adjusted_mode));
- if (!crtc_state->vrr.in_range)
- return;
- if (HAS_LRR(display))
+ if (crtc_state->vrr.in_range && HAS_LRR(display))
crtc_state->update_lrr = true;
- vmin = intel_vrr_compute_vmin(connector, adjusted_mode);
- vmax = intel_vrr_compute_vmax(connector, adjusted_mode);
-
- if (vmin >= vmax)
- return;
-
- if (crtc_state->uapi.vrr_enabled)
- intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
- else if (is_cmrr_frac_required(crtc_state) && is_edp)
- intel_vrr_compute_cmrr_timings(crtc_state);
- else
- intel_vrr_prepare_vrr_timings(crtc_state, vmin, vmax);
+ if (DISPLAY_VER(display) >= 20)
+ intel_vrr_compute_xe2lpd_timings(crtc_state, conn_state);
+ else {
+ int vmin = intel_vrr_compute_vmin(connector, adjusted_mode);
+ int vmax = intel_vrr_compute_vmax(connector, adjusted_mode);
+
+ if (!crtc_state->vrr.in_range || vmin >= vmax)
+ return;
+
+ if (crtc_state->uapi.vrr_enabled)
+ intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
+ else if (is_cmrr_frac_required(crtc_state) && is_edp)
+ intel_vrr_compute_cmrr_timings(crtc_state);
+ else
+ intel_vrr_prepare_vrr_timings(crtc_state, vmin, vmax);
+ }
if (HAS_AS_SDP(display)) {
crtc_state->vrr.vsync_start =
--
2.45.2
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