[PATCH 5/5] drm/i915/dp: Check link_m/link_n ratio limit in mode_valid

[Ankit Nautiyal]

Allow modes that will pass the link_m/link_n ratio limit for max link
rate, max lane and minimum bpp.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 19 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h     |  2 ++
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++++++
 3 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 150375ff9d5d..a0c54c9a91a0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1364,17 +1364,30 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 	return true;
 }
 
+bool intel_dp_check_m_n(struct intel_display *display, u16 link_bpp_x16,
+			int max_lanes, int target_clock, int max_link_clock)
+{
+	struct intel_link_m_n m_n;
+
+        return intel_link_compute_m_n(display, link_bpp_x16, max_lanes,
+				      target_clock, max_link_clock,
+				      intel_dp_bw_fec_overhead(true), &m_n) &&
+	       !intel_dp_bmg_bypass_m_n_limit(display, &m_n, PIPE_A);
+}
+
 static enum drm_mode_status
 intel_dp_mode_valid(struct drm_connector *_connector,
 		    struct drm_display_mode *mode)
 {
 	struct intel_connector *connector = to_intel_connector(_connector);
+	struct intel_display *display = to_intel_display(connector);
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 	const struct drm_display_mode *fixed_mode;
 	int target_clock = mode->clock;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
 	int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
+	u16 link_bpp_x16;
 	u16 dsc_max_compressed_bpp = 0;
 	u8 dsc_slice_count = 0;
 	enum drm_mode_status status;
@@ -1466,6 +1479,12 @@ intel_dp_mode_valid(struct drm_connector *_connector,
 	if (mode_rate > max_rate && !dsc)
 		return MODE_CLOCK_HIGH;
 
+	link_bpp_x16 = fxp_q4_from_int(dsc? dsc_max_compressed_bpp : 18);
+
+	if (intel_dp_check_m_n(display, link_bpp_x16, max_lanes,
+			       target_clock, max_link_clock))
+		return MODE_CLOCK_HIGH;
+
 	status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
 	if (status != MODE_OK)
 		return status;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index b09b088cdfc8..6d3520b19768 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -209,5 +209,7 @@ bool intel_dp_has_connector(struct intel_dp *intel_dp,
 bool intel_dp_bmg_bypass_m_n_limit(struct intel_display *display,
 				   struct intel_link_m_n *m_n,
 				   enum pipe pipe);
+bool intel_dp_check_m_n(struct intel_display *display, u16 link_bpp_x16,
+			int max_lanes, int target_clock, int max_link_clock);
 
 #endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b04418a009ae..5e402bf39708 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1429,6 +1429,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
 {
 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
 	struct intel_connector *intel_connector = to_intel_connector(connector);
+	struct intel_display *display = to_intel_display(intel_connector);
 	struct intel_dp *intel_dp = intel_connector->mst_port;
 	struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
 	struct drm_dp_mst_port *port = intel_connector->port;
@@ -1438,6 +1439,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
 	int ret;
 	bool dsc = false;
 	u16 dsc_max_compressed_bpp = 0;
+	u16 link_bpp_x16;
 	u8 dsc_slice_count = 0;
 	int target_clock = mode->clock;
 	int num_joined_pipes;
@@ -1531,7 +1533,15 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
 		return 0;
 	}
 
+	link_bpp_x16 = fxp_q4_from_int(dsc ? dsc_max_compressed_bpp : 18);
+
+	if (intel_dp_check_m_n(display, link_bpp_x16, max_lanes, target_clock, max_link_clock)) {
+		*status = MODE_CLOCK_HIGH;
+		return 0;
+	}
+
 	*status = intel_mode_valid_max_plane_size(dev_priv, mode, num_joined_pipes);
+
 	return 0;
 }
 
-- 
2.45.2