[PATCH 05/18] drm/i915/icl_dsi: Add support in crtc_state to configure dual link mode

[Ankit Nautiyal]

DSS control regs have bits to configure dual_link_mode. Add a new member
to configure dual link mode in splitter in crtc_state. Fill these
members in compute_config phase and use them later in
configure_dual_link_mode(). This will make the movement of the function
to intel_dss files easier and pave the way to configure dss ctl register
at one place.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        | 47 ++++++++++++-------
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 32 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5ad5011e1fee..3529d363d08e 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -274,17 +274,16 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 	}
 }
 
-static void configure_dual_link_mode(struct intel_encoder *encoder,
-				     const struct intel_crtc_state *pipe_config)
+static void configure_dual_link_mode(const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+	struct intel_display *display = to_intel_display(crtc_state);
+	u8 pixel_overlap = crtc_state->splitter.pixel_overlap;
 	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
 	u32 dss_ctl1;
 
-	/* FIXME: Move all DSS handling to intel_vdsc.c */
-	if (DISPLAY_VER(dev_priv) >= 12) {
-		struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+	/* FIXME: Move all DSS handling to intel_dss.c */
+	if (DISPLAY_VER(display) >= 12) {
+		struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 		dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
 		dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
@@ -293,34 +292,34 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
 		dss_ctl2_reg = DSS_CTL2;
 	}
 
-	dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
+	dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
 	dss_ctl1 |= SPLITTER_ENABLE;
 	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
-	dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
+	dss_ctl1 |= OVERLAP_PIXELS(pixel_overlap);
 
-	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
+	if (crtc_state->splitter.is_dual_link_front_back) {
 		const struct drm_display_mode *adjusted_mode =
-					&pipe_config->hw.adjusted_mode;
+					&crtc_state->hw.adjusted_mode;
 		u16 hactive = adjusted_mode->crtc_hdisplay;
 		u16 dl_buffer_depth;
 
 		dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
-		dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
+		dl_buffer_depth = hactive / 2 + pixel_overlap;
 
 		if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
-			drm_err(&dev_priv->drm,
+			drm_err(display->drm,
 				"DL buffer depth exceed max value\n");
 
 		dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
 		dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
-		intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
+		intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
 			     RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
 	} else {
 		/* Interleave */
 		dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
 	}
 
-	intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
+	intel_de_write(display, dss_ctl1_reg, dss_ctl1);
 }
 
 /* aka DSI 8X clock */
@@ -791,7 +790,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 		}
 
 		/* configure stream splitting */
-		configure_dual_link_mode(encoder, pipe_config);
+		configure_dual_link_mode(pipe_config);
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
@@ -1623,6 +1622,20 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 	return 0;
 }
 
+static void gen11_dsi_dss_compute_config(struct intel_dsi *intel_dsi,
+					 struct intel_crtc_state *crtc_state)
+{
+	if (!intel_dsi->dual_link)
+		return;
+
+	crtc_state->splitter.enable = true;
+
+	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+		crtc_state->splitter.is_dual_link_front_back = true;
+
+	crtc_state->splitter.pixel_overlap = intel_dsi->pixel_overlap;
+}
+
 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 				    struct intel_crtc_state *pipe_config,
 				    struct drm_connector_state *conn_state)
@@ -1673,6 +1686,8 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	if (is_cmd_mode(intel_dsi))
 		gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
 
+	gen11_dsi_dss_compute_config(intel_dsi, pipe_config);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 868ff8976ed9..333d84b0bf7b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1424,6 +1424,7 @@ struct intel_crtc_state {
 		bool enable;
 		u8 link_count;
 		u8 pixel_overlap;
+		bool is_dual_link_front_back;
 	} splitter;
 
 	/* for loading single buffered registers during vblank */
-- 
2.45.2