[PATCH v1 3/6] display/skl_watermark: Add WM0 latency

Mitul Golani mitulkumar.ajitkumar.golani at intel.com
Wed Sep 18 14:07:05 UTC 2024


Calculate WM0 prefill latency which accounts for maximum time
to fill data buffer up to watermark 0.
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 16 ++++++++++++++++
 drivers/gpu/drm/i915/display/skl_watermark.h |  1 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 6e1f04d5ef47..8223e3fb5aee 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2254,6 +2254,22 @@ static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
 	return wm0_lines;
 }
 
+int calc_wm0_prefill(struct intel_crtc_state *crtc_state)
+{
+	int linetime, cdclk_prefill, wm0_prefill;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+	linetime = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.htotal * 1000,
+				intel_crtc_dotclock(crtc_state));
+	cdclk_prefill = MIN(1, DIV_ROUND_UP(crtc_state->pixel_rate,
+					    2 * i915->display.cdclk.hw.cdclk));
+
+	wm0_prefill = 20 + (linetime * skl_max_wm0_lines(crtc_state) * cdclk_prefill);
+
+	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, wm0_prefill);
+}
+
 static int skl_max_wm_level_for_vblank(struct intel_crtc_state *crtc_state,
 				       int wm0_lines)
 {
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index e73baec94873..22ed17b00a71 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -23,6 +23,7 @@ struct skl_wm_level;
 
 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915);
 
+int calc_wm0_prefill(struct intel_crtc_state *crtc_state);
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
 void intel_sagv_post_plane_update(struct intel_atomic_state *state);
 bool intel_can_enable_sagv(struct drm_i915_private *i915,
-- 
2.46.0



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