[PATCH] drm/i915/vrr: Program EMP_AS_SDP_TL for DP AS SDP

[Ankit Nautiyal]

The register EMP_AS_SDP_TL (MTL) was introduced for configuring the
double buffering point and transmission line for
HDMI Video Timing Extended Metadata Packet (VTEMP) for VRR.
This was also intended to be configured for DP to HDMI2.1 PCON to
support VRR.

>From BMG and LNL+ onwards, this register was extended to Display Port
Adaptive Sync SDP to have a common register to configure double
buffering point and transmission line for both HDMI and DP VRR related
packets.

Currently, we do not support VRR for either native HDMI or via PCON.
However we need to configure this for DP SDP case. As per the spec,
program the register to set Vsync start as the double buffering point
for DP AS SDP.

Bspec:70984, 71197
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c      | 11 ++++++++++-
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |  6 ++++++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 633a66f6b73b..a52aca0a4c3f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -490,11 +490,20 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
 			       trans_vrr_ctl(crtc_state));
 
-	if (HAS_AS_SDP(display))
+	if (HAS_AS_SDP(display)) {
 		intel_de_write(display,
 			       TRANS_VRR_VSYNC(display, cpu_transcoder),
 			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
 			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));
+		/*
+		 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
+		 * double buffering point and transmission line for Adaptive Sync SDP.
+		 */
+		if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
+			intel_de_write(display,
+				       EMP_AS_SDP_TL(display, cpu_transcoder),
+				       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+	}
 }
 
 void intel_vrr_send_push(struct intel_dsb *dsb,
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 6ed0e0dc97e7..d2af1b6710bf 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -108,6 +108,12 @@
 #define VRR_VSYNC_START_MASK			REG_GENMASK(12, 0)
 #define VRR_VSYNC_START(vsync_start)		REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
 
+/* Common register for HDMI VTEMP and DP AS SDP */
+#define _EMP_AS_SDP_TL_A			0x60204
+#define EMP_AS_SDP_DB_TL_MASK			REG_GENMASK(12, 0)
+#define EMP_AS_SDP_TL(dev_priv, trans)		_MMIO_TRANS2(dev_priv, trans, _EMP_AS_SDP_TL_A)
+#define EMP_AS_SDP_DB_TL(db_transmit_line)	REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line))
+
 /*CMRR Registers*/
 
 #define _TRANS_CMRR_M_LO_A			0x604F0
-- 
2.45.2