[PATCH] Update seamless_m_n when drrs is enabled

[Nemesa Garg]

Signed-off-by: Nemesa Garg <nemesa.garg at intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index aeb14a5455fd..e4e767401f3a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2965,19 +2965,19 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 		intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
 	int pixel_clock;
 
-	/*
-	 * FIXME all joined pipes share the same transcoder.
-	 * Need to account for that when updating M/N live.
-	 */
-	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
-		pipe_config->update_m_n = true;
-
 	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
 		if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder))
 			intel_zero_m_n(&pipe_config->dp_m2_n2);
 		return;
 	}
 
+	/*
+         * FIXME all joined pipes share the same transcoder.
+         * Need to account for that when updating M/N live.
+         */
+        if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
+                pipe_config->update_m_n = true;
+
 	if (display->platform.ironlake || display->platform.sandybridge ||
 	    display->platform.ivybridge)
 		pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
-- 
2.25.1