[PATCH v1 6/6] drm/i915/vrr: Pause DC balancing for DSB commits
Mitul Golani
mitulkumar.ajitkumar.golani at intel.com
Mon Apr 21 10:06:58 UTC 2025
Pause the DMC DC balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +++
.../drm/i915/display/intel_display_types.h | 9 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 8 +-
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 65 +++++++++++
drivers/gpu/drm/i915/display/intel_dsb.c | 2 +-
drivers/gpu/drm/i915/display/intel_vblank.c | 2 +-
drivers/gpu/drm/i915/display/intel_vrr.c | 102 +++++++++++++++---
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 13 +++
8 files changed, 192 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index db524d01e574..bc8223a13ce7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7195,6 +7195,17 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
}
if (new_crtc_state->use_dsb) {
+ /*
+ * Pause the DMC DC balancing for the remainder of the
+ * commit so that vmin/vmax won't change after we've baked
+ * them into the DSB vblank evasion commands.
+ *
+ * FIXME maybe need a small delay here to make sure DMC has
+ * finished updating the values? Or we need a better DMC<->driver
+ * protocol that gives is real guarantees about that...
+ */
+ intel_pipedmc_dcb_disable(NULL, crtc);
+
if (intel_crtc_needs_color_update(new_crtc_state))
intel_color_commit_noarm(new_crtc_state->dsb_commit,
new_crtc_state);
@@ -7231,6 +7242,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state);
+ if (new_crtc_state->vrr.dc_balance.enable)
+ intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc);
intel_dsb_interrupt(new_crtc_state->dsb_commit);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0e06c71e9086..126d54e6a393 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1303,10 +1303,17 @@ struct intel_crtc_state {
/* Variable Refresh Rate state */
struct {
- bool enable, in_range, dc_balance;
+ bool enable, in_range;
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
u32 vsync_end, vsync_start;
+ struct {
+ bool enable;
+ u16 vmin, vmax;
+ u16 guardband, slope;
+ u16 max_increase, max_decrease;
+ u16 vblank_target;
+ } dc_balance;
} vrr;
/* Content Match Refresh Rate state */
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 17835b297f6d..ba0c1098f305 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1367,14 +1367,18 @@ void intel_dmc_debugfs_register(struct intel_display *display)
void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(crtc);
+ struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(crtc->pipe),
+ intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(display, cpu_transcoder),
PIPEDMC_ADAPTIVE_DCB_ENABLE);
}
void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(crtc);
+ struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(crtc->pipe), 0);
+ intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(display, cpu_transcoder), 0);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 1bf446f96a10..2f171c5dbb1c 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -103,4 +103,69 @@
#define DMC_WAKELOCK_CTL_REQ REG_BIT(31)
#define DMC_WAKELOCK_CTL_ACK REG_BIT(15)
+#define _PIPEDMC_DCB_CTL_A 0x5F1A0
+#define _PIPEDMC_DCB_CTL_B 0x5F5A0
+#define _PIPEDMC_DCB_CTL_C 0x5F9A0
+#define _PIPEDMC_DCB_CTL_D 0x5FDA0
+#define _PIPEDMC_DCB_CTL_E 0x551A0
+#define _PIPEDMC_DCB_CTL_F 0x555A0
+#define PIPEDMC_DCB_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_CTL_A)
+#define PIPEDMC_ADAPTIVE_DCB_ENABLE REG_BIT(31)
+
+#define _PIPEDMC_DCB_VBLANK_A 0x5F1BC
+#define _PIPEDMC_DCB_VBLANK_B 0x5F5BC
+#define _PIPEDMC_DCB_VBLANK_C 0x5F9BC
+#define _PIPEDMC_DCB_VBLANK_D 0x5FDBC
+#define _PIPEDMC_DCB_VBLANK_E 0x551BC
+#define _PIPEDMC_DCB_VBLANK_F 0x555BC
+#define PIPEDMC_DCB_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VBLANK_A)
+
+#define _PIPEDMC_DCB_SLOPE_A 0x5F1B8
+#define _PIPEDMC_DCB_SLOPE_B 0x5F5B8
+#define _PIPEDMC_DCB_SLOPE_C 0x5F9B8
+#define _PIPEDMC_DCB_SLOPE_D 0x5FDB8
+#define _PIPEDMC_DCB_SLOPE_E 0x551B8
+#define _PIPEDMC_DCB_SLOPE_F 0x555B8
+#define PIPEDMC_DCB_SLOPE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_SLOPE_A)
+
+#define _PIPEDMC_DCB_GUARDBAND_A 0x5F1B4
+#define _PIPEDMC_DCB_GUARDBAND_B 0x5F5B4
+#define _PIPEDMC_DCB_GUARDBAND_C 0x5F9B4
+#define _PIPEDMC_DCB_GUARDBAND_D 0x5FDB4
+#define _PIPEDMC_DCB_GUARDBAND_E 0x551B4
+#define _PIPEDMC_DCB_GUARDBAND_F 0x555B4
+#define PIPEDMC_DCB_GUARDBAND(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_GUARDBAND_A)
+
+#define _PIPEDMC_DCB_MAX_INCREASE_A 0x5F1AC
+#define _PIPEDMC_DCB_MAX_INCREASE_B 0x5F5AC
+#define _PIPEDMC_DCB_MAX_INCREASE_C 0x5F9AC
+#define _PIPEDMC_DCB_MAX_INCREASE_D 0x5FDAC
+#define _PIPEDMC_DCB_MAX_INCREASE_E 0x551AC
+#define _PIPEDMC_DCB_MAX_INCREASE_F 0x555AC
+#define PIPEDMC_DCB_MAX_INCREASE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_MAX_INCREASE_A)
+
+#define _PIPEDMC_DCB_MAX_DECREASE_A 0x5F1B0
+#define _PIPEDMC_DCB_MAX_DECREASE_B 0x5F5B0
+#define _PIPEDMC_DCB_MAX_DECREASE_C 0x5F9B0
+#define _PIPEDMC_DCB_MAX_DECREASE_D 0x5FDB0
+#define _PIPEDMC_DCB_MAX_DECREASE_E 0x551B0
+#define _PIPEDMC_DCB_MAX_DECREASE_F 0x555B0
+#define PIPEDMC_DCB_MAX_DECREASE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_MAX_DECREASE_A)
+
+#define _PIPEDMC_DCB_VMIN_A 0x5F1A4
+#define _PIPEDMC_DCB_VMIN_B 0x5F5A4
+#define _PIPEDMC_DCB_VMIN_C 0x5F9A4
+#define _PIPEDMC_DCB_VMIN_D 0x5FDA4
+#define _PIPEDMC_DCB_VMIN_E 0x551A4
+#define _PIPEDMC_DCB_VMIN_F 0x555A4
+#define PIPEDMC_DCB_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VMIN_A)
+
+#define _PIPEDMC_DCB_VMAX_A 0x5F1A8
+#define _PIPEDMC_DCB_VMAX_B 0x5F5A8
+#define _PIPEDMC_DCB_VMAX_C 0x5F9A8
+#define _PIPEDMC_DCB_VMAX_D 0x5FDA8
+#define _PIPEDMC_DCB_VMAX_E 0x551A8
+#define _PIPEDMC_DCB_VMAX_F 0x555A8
+#define PIPEDMC_DCB_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VMAX_A)
+
#endif /* __INTEL_DMC_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index ed27cbff44fc..ffd10ee96e29 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -577,7 +577,7 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
if (crtc_state->has_psr)
intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
- if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance) {
+ if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
int vblank_delay = intel_vrr_vblank_delay(crtc_state);
int vmin_vblank_start, vmax_vblank_start;
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 9b63e4217881..eb74d08d6690 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -647,7 +647,7 @@ static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
bool is_push_sent = intel_vrr_is_push_sent(crtc_state);
int vblank_start;
- if (!crtc_state->vrr.dc_balance) {
+ if (!crtc_state->vrr.dc_balance.enable) {
if (is_push_sent)
return intel_vrr_vmin_vblank_start(crtc_state);
else
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 03405c274b8c..81227510da1a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,12 +9,17 @@
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_dmc.h"
+#include "intel_dmc_regs.h"
#include "intel_dp.h"
#include "intel_vrr.h"
#include "intel_vrr_regs.h"
-#define FIXED_POINT_PRECISION 100
-#define CMRR_PRECISION_TOLERANCE 10
+#define FIXED_POINT_PRECISION 100
+#define CMRR_PRECISION_TOLERANCE 10
+#define DCB_CORRECTION_SENSITIVITY 30
+#define DCB_CORRECTION_AGGRESSIVENESS 1000
+#define ADAPTIVE_BALANCE_BLANK_PERCENT 50
bool intel_vrr_is_capable(struct intel_connector *connector)
{
@@ -299,6 +304,7 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
intel_vrr_fixed_rr_vmax(crtc_state) - 1);
intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
intel_vrr_fixed_rr_flipline(crtc_state) - 1);
+
}
static
@@ -408,6 +414,16 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
(crtc_state->hw.adjusted_mode.crtc_vtotal -
crtc_state->hw.adjusted_mode.vsync_end);
}
+
+ if (crtc_state->vrr.dc_balance.enable) {
+ crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
+ crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
+ crtc_state->vrr.dc_balance.max_increase = crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+ crtc_state->vrr.dc_balance.max_decrease = crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+ crtc_state->vrr.dc_balance.guardband = DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax * DCB_CORRECTION_SENSITIVITY, 100);
+ crtc_state->vrr.dc_balance.slope = DIV_ROUND_UP(DCB_CORRECTION_AGGRESSIVENESS * 10, crtc_state->vrr.dc_balance.guardband);
+ crtc_state->vrr.dc_balance.vblank_target = DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) * ADAPTIVE_BALANCE_BLANK_PERCENT, 100);
+ }
}
void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
@@ -576,7 +592,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display)
void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 ctl;
if (!crtc_state->vrr.enable)
return;
@@ -587,33 +605,73 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
crtc_state->vrr.vmax - 1);
intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
crtc_state->vrr.flipline - 1);
+ if (!intel_vrr_always_use_vrr_tg(display))
+ intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN);
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
TRANS_PUSH_EN);
- if (!intel_vrr_always_use_vrr_tg(display)) {
- if (crtc_state->cmrr.enable) {
- intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
- VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
- trans_vrr_ctl(crtc_state));
- } else {
- intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
- VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
- }
+ ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
+ if (crtc_state->cmrr.enable)
+ ctl |= VRR_CTL_CMRR_ENABLE;
+ if (crtc_state->vrr.dc_balance.enable)
+ ctl |= VRR_CTL_DCB_ADJ_ENABLE;
+
+ intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
+
+ if (crtc_state->vrr.dc_balance.enable) {
+ intel_de_write(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder),
+ crtc_state->vrr.dc_balance.vmin - 1);
+ intel_de_write(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder),
+ crtc_state->vrr.dc_balance.vmax - 1);
+ intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder),
+ crtc_state->vrr.dc_balance.max_increase);
+ intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder),
+ crtc_state->vrr.dc_balance.max_decrease);
+ intel_de_write(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder),
+ crtc_state->vrr.dc_balance.guardband);
+ intel_de_write(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder),
+ crtc_state->vrr.dc_balance.slope);
+ intel_de_write(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder),
+ crtc_state->vrr.dc_balance.vblank_target);
+ /* FIXME reset counters? */
+ intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, cpu_transcoder),
+ ADAPTIVE_SYNC_COUNTER_EN);
+ /* FIMXE configure pipedmc DC balance parameters somewhere */
+ intel_pipedmc_dcb_enable(NULL, crtc);
}
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
{
struct intel_display *display = to_intel_display(old_crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+ u32 ctl;
if (!old_crtc_state->vrr.enable)
return;
+ if (old_crtc_state->vrr.dc_balance.enable) {
+ intel_pipedmc_dcb_disable(NULL, crtc);
+ intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, cpu_transcoder), 0);
+ intel_de_write(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder), 0);
+ intel_de_write(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder), 0);
+ intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder), 0);
+ intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder), 0);
+ intel_de_write(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder), 0);
+ intel_de_write(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder), 0);
+ intel_de_write(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder), 0);
+
+ }
+
+ ctl = trans_vrr_ctl(old_crtc_state);
+ if (intel_vrr_always_use_vrr_tg(display))
+ ctl |= VRR_CTL_VRR_ENABLE;
+
+ intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
+
if (!intel_vrr_always_use_vrr_tg(display)) {
- intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
- trans_vrr_ctl(old_crtc_state));
intel_de_wait_for_clear(display,
TRANS_VRR_STATUS(display, cpu_transcoder),
VRR_STATUS_VRR_EN_LIVE, 1000);
@@ -694,6 +752,16 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
TRANS_CMRR_M_HI(display, cpu_transcoder));
}
+ if (trans_vrr_ctl & VRR_CTL_DCB_ADJ_ENABLE) {
+ crtc_state->vrr.dc_balance.vmin = intel_de_read(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder)) + 1;
+ crtc_state->vrr.dc_balance.vmax = intel_de_read(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder)) + 1;
+ crtc_state->vrr.dc_balance.max_increase = intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder));
+ crtc_state->vrr.dc_balance.max_decrease = intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder));
+ crtc_state->vrr.dc_balance.guardband = intel_de_read(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder));
+ crtc_state->vrr.dc_balance.slope = intel_de_read(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder));
+ crtc_state->vrr.dc_balance.vblank_target = intel_de_read(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder));
+ }
+
if (DISPLAY_VER(display) >= 13)
crtc_state->vrr.guardband =
REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
@@ -753,7 +821,7 @@ int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_sta
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 tmp;
- tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder));
+ tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(display, cpu_transcoder));
if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
return -1;
@@ -768,7 +836,7 @@ int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_sta
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 tmp;
- tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder));
+ tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(display, cpu_transcoder));
if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
return -1;
@@ -783,7 +851,7 @@ int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_st
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 tmp;
- tmp = intel_de_read(display, TRANS_VRR_FLIPLINE_DCB(cpu_transcoder));
+ tmp = intel_de_read(display, TRANS_VRR_FLIPLINE_DCB(display, cpu_transcoder));
return intel_vrr_vblank_start(crtc_state,
REG_FIELD_GET(VRR_FLIPLINE_DCB_MASK, tmp) + 1);
@@ -795,7 +863,7 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 tmp;
- tmp = intel_de_read(display, TRANS_VRR_VMAX_DCB(cpu_transcoder));
+ tmp = intel_de_read(display, TRANS_VRR_VMAX_DCB(display, cpu_transcoder));
return intel_vrr_vblank_start(crtc_state,
REG_FIELD_GET(VRR_VMAX_DCB_MASK, tmp) + 1);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 0f7476bf5696..54055a8ec04e 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -28,8 +28,20 @@
#define TRANS_VRR_DCB_ADJ_VMAX_CFG(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
trans, \
_TRANS_VRR_DCB_ADJ_VMAX_CFG_A)
+
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_C 0x624C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_D 0x634C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_E 0x6B4C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_F 0x6C4C0
+#define TRANS_ADAPTIVE_SYNC_DCB_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
+ trans, \
+ _TRANS_ADAPTIVE_SYNC_DCB_CTL_A)
+
#define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24)
#define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0)
+#define ADAPTIVE_SYNC_COUNTER_EN REG_BIT(31)
#define _TRANS_VRR_FLIPLINE_DCB_A 0x60418
#define _TRANS_VRR_FLIPLINE_DCB_B 0x61418
@@ -57,6 +69,7 @@
#define _TRANS_VRR_CTL_D 0x63420
#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
#define VRR_CTL_VRR_ENABLE REG_BIT(31)
+#define VRR_CTL_DCB_ADJ_ENABLE REG_BIT(28)
#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
--
2.48.1
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