[PATCH] drm/dp: Add quirk for panel with HBR3 without TPS4

[Ankit Nautiyal]

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/display/drm_dp_helper.c |  2 ++
 drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++++++++++++---
 include/drm/display/drm_dp_helper.h     |  8 ++++++++
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 57828f2b7b5a..eb267159b646 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2519,6 +2519,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
 	{ OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
 	/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
 	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
+	/* MediaTek panel */
+	{ OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBR3_WITHOUT_TPS4) },
 };
 
 #undef OUI
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 607aea1bf6fa..97554193b400 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -170,6 +170,26 @@ int intel_dp_link_symbol_clock(int rate)
 	return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
 }
 
+static bool detected_hbr3_tps4_quirk(struct intel_dp *intel_dp)
+{
+	struct intel_connector *connector = intel_dp->attached_connector;
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct drm_dp_aux *aux = &intel_dp->aux;
+	struct drm_dp_desc desc;
+
+	if (drm_dp_read_desc(aux, &desc, drm_dp_is_branch(intel_dp->dpcd)) < 0)
+		return false;
+
+	if (!drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_HBR3_WITHOUT_TPS4))
+		return false;
+
+	drm_dbg_kms(display->drm,
+		    "[CONNECTOR:%d:%s] HBR3 without TPS4 quirk detected\n",
+		    connector->base.base.id, connector->base.name);
+
+	return true;
+}
+
 static int max_dprx_rate(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
@@ -186,7 +206,7 @@ static int max_dprx_rate(struct intel_dp *intel_dp)
 	 * HBR3 without TPS4, and are unable to produce a stable
 	 * output. Reject HBR3 when TPS4 is not available.
 	 */
-	if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {
+	if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd) &&!detected_hbr3_tps4_quirk(intel_dp)) {
 		drm_dbg_kms(display->drm,
 			    "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n",
 			    encoder->base.base.id, encoder->base.name);
@@ -4220,13 +4240,12 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
 			 * HBR3 without TPS4, and are unable to produce a stable
 			 * output. Reject HBR3 when TPS4 is not available.
 			 */
-			if (rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {
+			if (rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd) &&!detected_hbr3_tps4_quirk(intel_dp)) {
 				drm_dbg_kms(display->drm,
 					    "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n",
 					    encoder->base.base.id, encoder->base.name);
 				break;
 			}
-
 			intel_dp->sink_rates[i] = rate;
 		}
 		intel_dp->num_sink_rates = i;
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index d9614e2c8939..77805b0005f8 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -809,6 +809,14 @@ enum drm_dp_quirk {
 	 * requires enabling DSC.
 	 */
 	DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
+
+	/**
+	 * @DP_DPCD_QUIRK_HBR3_WITHOUT_TPS4:
+	 *
+	 * The device supports HBR3 without TPS4, which is against the DP1.4 spec
+	 * that mandates TPS4 with HBR3.
+	 */
+	DP_DPCD_QUIRK_HBR3_WITHOUT_TPS4,
 };
 
 /**
-- 
2.45.2