[PATCH 0/6] Account for DSC bubble overhead for horizontal slices

[Ankit Nautiyal]

When dsc is enabled on a pipe, the pipe pixel rate input to the
cdclk frequency and pipe joining calculation needs an adjustment to
account for compression overhead "bubbles" added at each horizontal
slice boundary. This overhead was always there even for earlier
platforms, but was not accounted.

Currently the number of joined pipes required is computed much earlier
than the policy to use DSC both in mode valid phase for each mode and
for compute config phase for a given mode.

Due to this the overhead for DSC bubbles cannot be determined at the
time of computing number of joined pipes, which may lead to issues.

This series is an attempt to refactor the sequence of steps for
determining the number of pipes to be joined and policy of DSC.

In the first few patches the mode_valid step is refactored to make way for
accounting for this DSC bubble overhead. The last two patches account for
this overhead during cdclk calculations and in mode_valid step for DP.

#TODO: Account for the above overhead in DP compute_config phase.

Ankit Nautiyal (6):
  drm/i915/dp: Early reject bad hdisplay in intel_dp_mode_valid
  drm/i915/dp: Extract code to get slice and bpp to a separate function
  drm/i915/dp: Move num_joined_pipes and related checks together
  drm/i915/dp: Rework pipe joiner logic in mode_valid
  drm/i915/vdsc: Account for overhead bubbles in horizontal slices
  drm/i915/dp: Account for dsc bubbles overhead in intel_dp_mode_valid()

 drivers/gpu/drm/i915/display/intel_dp.c   | 156 +++++++++++++++-------
 drivers/gpu/drm/i915/display/intel_vdsc.c |  44 +++++-
 drivers/gpu/drm/i915/display/intel_vdsc.h |   2 +
 3 files changed, 148 insertions(+), 54 deletions(-)

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2.45.2