[PATCH 07/13] drm/i915/display: Remove vrr.enable and instead check vrr.mode != NONE
Ankit Nautiyal
ankit.k.nautiyal at intel.com
Sat Feb 1 09:31:36 UTC 2025
Since we now have vrr.mode to track the mode in which the VRR timing
generator is running, we no longer need member vrr.enable.
Replace the check for vrr.enable and use a helper to check
vrr.mode != NONE.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
.../drm/i915/display/intel_crtc_state_dump.c | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display.c | 11 +++++------
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 2 +-
.../drm/i915/display/intel_modeset_setup.c | 3 ++-
drivers/gpu/drm/i915/display/intel_psr.c | 5 +++--
drivers/gpu/drm/i915/display/intel_vrr.c | 19 ++++++++++---------
drivers/gpu/drm/i915/display/intel_vrr.h | 1 +
drivers/gpu/drm/i915/display/skl_watermark.c | 3 ++-
11 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 36076e8d639b..56a43f3fc7f6 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -293,7 +293,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
pipe_config->framestart_delay, pipe_config->msa_timing_delay);
drm_printf(&p, "vrr: %s, vmin: %d, vmax: %d, flipline: %d, pipeline full: %d, guardband: %d vsync start: %d, vsync end: %d\n",
- str_yes_no(pipe_config->vrr.enable),
+ str_yes_no(intel_vrr_is_enabled(pipe_config)),
pipe_config->vrr.vmin, pipe_config->vrr.vmax, pipe_config->vrr.flipline,
pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
pipe_config->vrr.vsync_start, pipe_config->vrr.vsync_end);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index dc319f37b1be..f440299da637 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -77,6 +77,7 @@
#include "intel_tc.h"
#include "intel_vdsc.h"
#include "intel_vdsc_regs.h"
+#include "intel_vrr.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
@@ -2280,7 +2281,7 @@ static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel
{
struct intel_display *display = to_intel_display(intel_dp);
- if (!crtc_state->vrr.enable)
+ if (!intel_vrr_is_enabled(crtc_state))
return;
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 861929aea4b9..ba7194add02c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1130,8 +1130,8 @@ static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
if (!new_crtc_state->hw.active)
return false;
- return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
- (new_crtc_state->vrr.enable &&
+ return is_enabling(vrr.mode, old_crtc_state, new_crtc_state) ||
+ (intel_vrr_is_enabled(new_crtc_state) &&
(new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
@@ -1147,8 +1147,8 @@ bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
if (!old_crtc_state->hw.active)
return false;
- return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
- (old_crtc_state->vrr.enable &&
+ return is_disabling(vrr.mode, old_crtc_state, new_crtc_state) ||
+ (intel_vrr_is_enabled(old_crtc_state) &&
(new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
vrr_params_changed(old_crtc_state, new_crtc_state)));
}
@@ -5802,7 +5802,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(splitter.pixel_overlap);
if (!fastset) {
- PIPE_CONF_CHECK_BOOL(vrr.enable);
PIPE_CONF_CHECK_X(vrr.mode);
PIPE_CONF_CHECK_I(vrr.vmin);
PIPE_CONF_CHECK_I(vrr.vmax);
@@ -7280,7 +7279,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
if (intel_crtc_vrr_enabling(state, crtc) ||
new_crtc_state->update_m_n || new_crtc_state->update_lrr)
intel_crtc_update_active_timings(new_crtc_state,
- new_crtc_state->vrr.enable);
+ intel_vrr_is_enabled(new_crtc_state));
/*
* We usually enable FIFO underrun interrupts as part of the
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3195c9f33028..c553274c2af8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1308,7 +1308,7 @@ struct intel_crtc_state {
/* Variable Refresh Rate state */
struct {
- bool enable, in_range;
+ bool in_range;
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
u32 vsync_end, vsync_start;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 80214a559013..7864a4908399 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2924,7 +2924,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- if (pipe_config->vrr.enable)
+ if (intel_vrr_is_enabled(pipe_config))
return false;
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 2f2812c23972..78be517352e6 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -106,7 +106,7 @@ static bool pre_commit_is_vrr_active(struct intel_atomic_state *state,
return false;
/* VRR will have been disabled during intel_pre_plane_update() */
- return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc);
+ return intel_vrr_is_enabled(old_crtc_state) && !intel_crtc_vrr_disabling(state, crtc);
}
static int dsb_vblank_delay(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 10cdfdad82e4..9b18599d8b7e 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -31,6 +31,7 @@
#include "intel_pmdemand.h"
#include "intel_tc.h"
#include "intel_vblank.h"
+#include "intel_vrr.h"
#include "intel_wm.h"
#include "skl_watermark.h"
@@ -859,7 +860,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
crtc_state->inherited = true;
intel_crtc_update_active_timings(crtc_state,
- crtc_state->vrr.enable);
+ intel_vrr_is_enabled(crtc_state));
intel_crtc_copy_hw_to_uapi_state(crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2bdb6c9c2283..6fcb8d4a1c39 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -44,6 +44,7 @@
#include "intel_psr.h"
#include "intel_psr_regs.h"
#include "intel_snps_phy.h"
+#include "intel_vrr.h"
#include "skl_universal_plane.h"
/**
@@ -1484,7 +1485,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
}
/* Wa_16011303918:adl-p */
- if (crtc_state->vrr.enable &&
+ if (intel_vrr_is_enabled(crtc_state) &&
IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
drm_dbg_kms(display->drm,
"PSR2 not enabled, not compatible with HW stepping + VRR\n");
@@ -1689,7 +1690,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
/*
* Currently PSR/PR doesn't work reliably with VRR enabled.
*/
- if (crtc_state->vrr.enable)
+ if (intel_vrr_is_enabled(crtc_state))
return;
crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index ded5466c5214..5c00eef64bfd 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -225,7 +225,6 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
static
void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
{
- crtc_state->vrr.enable = true;
crtc_state->cmrr.enable = true;
crtc_state->vrr.mode = INTEL_VRRTG_MODE_CMRR;
/*
@@ -243,7 +242,6 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
static
void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
{
- crtc_state->vrr.enable = true;
crtc_state->vrr.mode = INTEL_VRRTG_MODE_VRR;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
@@ -277,6 +275,11 @@ int intel_vrr_compute_vmax(struct intel_connector *connector,
return vmax;
}
+bool intel_vrr_is_enabled(const struct intel_crtc_state *crtc_state)
+{
+ return crtc_state->vrr.mode != INTEL_VRRTG_MODE_NONE;
+}
+
void
intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
@@ -433,7 +436,7 @@ void intel_vrr_send_push(struct intel_dsb *dsb,
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (!crtc_state->vrr.enable)
+ if (!intel_vrr_is_enabled(crtc_state))
return;
if (dsb)
@@ -452,7 +455,7 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (!crtc_state->vrr.enable)
+ if (!intel_vrr_is_enabled(crtc_state))
return false;
return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND;
@@ -463,7 +466,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (!crtc_state->vrr.enable)
+ if (!intel_vrr_is_enabled(crtc_state))
return;
intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
@@ -484,7 +487,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
struct intel_display *display = to_intel_display(old_crtc_state);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- if (!old_crtc_state->vrr.enable)
+ if (!intel_vrr_is_enabled(old_crtc_state))
return;
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
@@ -504,8 +507,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
trans_vrr_ctl = intel_de_read(display,
TRANS_VRR_CTL(display, cpu_transcoder));
- crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
-
if (HAS_CMRR(display) && trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) {
crtc_state->cmrr.enable = true;
crtc_state->vrr.mode = INTEL_VRRTG_MODE_CMRR;
@@ -546,6 +547,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
}
}
- if (crtc_state->vrr.enable)
+ if (intel_vrr_is_enabled(crtc_state))
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 899cbf40f880..736bf7777abe 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -33,5 +33,6 @@ int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state);
int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);
int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state);
+bool intel_vrr_is_enabled(const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_VRR_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 45fe4aaeb450..1e08c0fb03ca 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -23,6 +23,7 @@
#include "intel_fb.h"
#include "intel_fixed.h"
#include "intel_pcode.h"
+#include "intel_vrr.h"
#include "intel_wm.h"
#include "skl_universal_plane_regs.h"
#include "skl_watermark.h"
@@ -3012,7 +3013,7 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
- if (!new_crtc_state->vrr.enable ||
+ if (!intel_vrr_is_enabled(new_crtc_state) ||
(new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax &&
new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline))
fixed_refresh_rate = true;
--
2.45.2
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