[PATCH 19/27] drm/i915/vrr: Always set vrr vmax/vmin/flipline in vrr_{enable/disable}

[Ankit Nautiyal]

Currently, if panel supports VRR, irrespective of whether the VRR property
is set by the user or not, we set the flipline, vmin and vmax to
appropriate values in anticipation of VRR. When the user sets the VRR
property, all the timings are in place and we just need to enable VRR.

To work seamlessly between variable and fixed timings,
intel_vrr_{enable,disable}() should just flip between the fixed and
variable timings in vmin/flipline/vmax.
The idea is to just do this for all the platforms, regarless of whether
we also toggle the VRR_CTL enable bit there.

To achieve this avoid preparing for VRR timings in compute config phase
and move the helper to write vrr timings to vrr_{enable/disable}.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 2 --
 drivers/gpu/drm/i915/display/intel_vrr.c     | 6 ++++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 782acbc39de8..c5f884956a20 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1764,8 +1764,6 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 	}
 
 	intel_set_transcoder_timings(crtc_state);
-	if (HAS_VRR(dev_priv))
-		intel_vrr_set_transcoder_timings(crtc_state);
 
 	if (cpu_transcoder != TRANSCODER_EDP)
 		intel_de_write(dev_priv, TRANS_MULT(dev_priv, cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 56e5b5602c7d..c0eedbc1bf69 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -338,8 +338,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
 	else if (is_cmrr_frac_required(crtc_state) && is_edp)
 		intel_vrr_compute_cmrr_timings(crtc_state);
-	else
-		intel_vrr_prepare_vrr_timings(crtc_state, vmin, vmax);
 
 	if (intel_dp->as_sdp_supported && intel_vrrtg_is_enabled(crtc_state)) {
 		crtc_state->vrr.vsync_start =
@@ -476,6 +474,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	if (!intel_vrrtg_is_enabled(crtc_state))
 		return;
 
+	intel_vrr_set_transcoder_timings(crtc_state);
+
 	if (intel_vrr_use_push(crtc_state))
 		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
 			       TRANS_PUSH_EN);
@@ -504,6 +504,8 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 	if (!intel_vrrtg_is_enabled(old_crtc_state))
 		return;
 
+	intel_vrr_set_transcoder_timings(old_crtc_state);
+
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
 		       trans_vrr_ctl(old_crtc_state));
 	intel_de_wait_for_clear(display,
-- 
2.45.2