[PATCH 26/27] drm/i915/vrr: Always use VRR timing generator for MTL+

[Ankit Nautiyal]

Currently VRR timing generator is used only when VRR is enabled by
userspace. From MTL+, gradually move away from older timing
generator and use VRR timing generator for fixed refresh rate also.

In such a case, Flipline Vmin and Vmax all are set to the Vtotal of the
mode, which effectively makes the VRR timing generator work in
fixed refresh rate mode.
The MSA Vtotal is derived from Vmax register.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 27 ++++++++++++++++++++----
 1 file changed, 23 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 6f5091bd8aad..e68e36959866 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -256,6 +256,23 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
 
+static
+void intel_vrr_compute_fixed_rr_timings(struct intel_crtc_state *crtc_state)
+{
+	/*
+	 * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
+	 * Vtotal value. The sink uses MSA timings for the fixed refresh rate
+	 * mode. The HW prepares the Vtotal for the MSA from the VMAX register.
+	 * Since the MSA Vtotal is one-based while Vmax is zero-based we need to
+	 * take care of this while setting Vtotal value.
+	 */
+	crtc_state->vrr.vmin = crtc_state->hw.adjusted_mode.vtotal - 1;
+	crtc_state->vrr.vmax = crtc_state->vrr.vmin;
+	crtc_state->vrr.flipline = crtc_state->vrr.vmax;
+	crtc_state->vrr.mode = INTEL_VRRTG_MODE_FIXED_RR;
+	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+}
+
 static
 void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state, int vmin, int vmax)
 {
@@ -310,6 +327,9 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	int vmin, vmax;
 
+	if (!HAS_VRR(display))
+		return;
+
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 		return;
 
@@ -324,13 +344,12 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	vmin = intel_vrr_compute_vmin(crtc_state);
 	vmax = intel_vrr_compute_vmax(connector, adjusted_mode);
 
-	if (vmin >= vmax)
-		return;
-
-	if (crtc_state->uapi.vrr_enabled)
+	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
 		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
 	else if (is_cmrr_frac_required(crtc_state) && is_edp)
 		intel_vrr_compute_cmrr_timings(crtc_state);
+	else if (DISPLAY_VER(display) >= 14)
+		intel_vrr_compute_fixed_rr_timings(crtc_state);
 
 	if (intel_dp->as_sdp_supported && intel_vrrtg_is_enabled(crtc_state)) {
 		crtc_state->vrr.vsync_start =
-- 
2.45.2