[PATCH] ECC workaround
Nemesa Garg
nemesa.garg at intel.com
Wed Jul 16 18:31:21 UTC 2025
Signed-off-by: Nemesa Garg <nemesa.garg at intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 52 ++++++++++++++++++-
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/skl_scaler.c | 22 ++++++++
drivers/gpu/drm/i915/display/skl_scaler.h | 3 ++
4 files changed, 77 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 456fc4b04cda..312e1cf71e22 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1648,6 +1648,30 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
hsw_set_transconf(crtc_state);
}
+static void skl_scaler_ecc_unmask_work(struct work_struct *work)
+{
+ struct delayed_work *delayed_work = to_delayed_work(work);
+ struct intel_atomic_state *state =
+ container_of(delayed_work, struct intel_atomic_state, ecc_work);
+
+ struct intel_display *display = to_intel_display(state);
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc *crtc;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ struct intel_crtc_scaler_state *scaler_state =
+ &new_crtc_state->scaler_state;
+ int id = scaler_state->scaler_id;
+
+ if (!new_crtc_state->pch_pfit.enabled && id == -1)
+ return;
+
+ intel_de_write_fw(display, SKL_PS_ECC_STAT(crtc->pipe, id), 1);
+ intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, 0);
+ }
+}
+
static void hsw_crtc_enable(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -1701,11 +1725,21 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
if (glk_need_scaler_clock_gating_wa(pipe_crtc_state))
glk_pipe_scaler_clock_gating_wa(pipe_crtc, true);
+ if (DISPLAY_VER(display) == 13) {
+ INIT_DELAYED_WORK(&state->ecc_work, skl_scaler_ecc_unmask_work);
+ skl_scaler_ecc_mask(state, pipe_crtc);
+ }
+
if (DISPLAY_VER(display) >= 9)
skl_pfit_enable(pipe_crtc_state);
else
ilk_pfit_enable(pipe_crtc_state);
+ if (DISPLAY_VER(display) == 13) {
+ schedule_delayed_work(&state->ecc_work,
+ usecs_to_jiffies(intel_get_frame_time_us(new_crtc_state) * 1));
+ }
+
/*
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
@@ -1809,6 +1843,8 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
intel_dmc_disable_pipe(old_pipe_crtc_state);
}
+
+ cancel_delayed_work_sync(&state->ecc_work);
}
/* Prefer intel_encoder_is_combo() */
@@ -6563,7 +6599,8 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
}
}
-static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
+static void intel_pipe_fastset(struct intel_atomic_state *state,
+ const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
struct intel_display *display = to_intel_display(new_crtc_state);
@@ -6579,6 +6616,11 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
*/
intel_set_pipe_src_size(new_crtc_state);
+ if (DISPLAY_VER(display) == 13) {
+ INIT_DELAYED_WORK(&state->ecc_work, skl_scaler_ecc_unmask_work);
+ skl_scaler_ecc_mask(state, crtc);
+ }
+
/* on skylake this is done by detaching scalers */
if (DISPLAY_VER(display) >= 9) {
if (new_crtc_state->pch_pfit.enabled)
@@ -6590,6 +6632,12 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
ilk_pfit_disable(old_crtc_state);
}
+ /* WA_14011503117: adlp_p */
+ if (DISPLAY_VER(display) == 13) {
+ schedule_delayed_work(&state->ecc_work,
+ usecs_to_jiffies(intel_get_frame_time_us(new_crtc_state) * 1));
+ }
+
/*
* The register is supposedly single buffered so perhaps
* not 100% correct to do this here. But SKL+ calculate
@@ -6634,7 +6682,7 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
bdw_set_pipe_misc(NULL, new_crtc_state);
if (intel_crtc_needs_fastset(new_crtc_state))
- intel_pipe_fastset(old_crtc_state, new_crtc_state);
+ intel_pipe_fastset(state, old_crtc_state, new_crtc_state);
}
intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ce45261c4a8f..7246e52715a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -614,6 +614,8 @@ struct intel_atomic_state {
bool rps_interactive;
struct work_struct cleanup_work;
+
+ struct delayed_work ecc_work;
};
struct intel_plane_state {
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 4cc55f4e1f9f..726246de2d11 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -938,3 +938,25 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
else
scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
}
+
+void skl_scaler_ecc_mask(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(state);
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (!crtc_state->pch_pfit.enabled)
+ return;
+
+ intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
+}
+
+u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->hw.active)
+ return 0;
+
+ return DIV_ROUND_UP(1000 * 1000,
+ drm_mode_vrefresh(&crtc_state->hw.adjusted_mode));
+}
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h
index 692716dd7616..4b3aa5a76d2e 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.h
+++ b/drivers/gpu/drm/i915/display/skl_scaler.h
@@ -44,4 +44,7 @@ skl_scaler_mode_valid(struct intel_display *display,
enum intel_output_format output_format,
int num_joined_pipes);
+void skl_scaler_ecc_mask(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state);
#endif
--
2.25.1
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