[PATCH 16/16] drm/i915/display: Avoid use of VTOTAL.Vtotal bits
Ankit Nautiyal
ankit.k.nautiyal at intel.com
Sat Mar 22 04:59:22 UTC 2025
For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
bits are not required. Since the support for these bits is going to
be deprecated in upcoming platforms, avoid writing these bits for the
platforms that do not use legacy Timing Generator.
Since for these platforms TRAN_VMIN is always filled with crtc_vtotal,
use TRAN_VRR_VMIN to get the vtotal for adjusted_mode.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 66 +++++++++++++++-----
1 file changed, 52 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ae1dc32044fb..08d04b25844d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -122,6 +122,7 @@
#include "intel_vdsc_regs.h"
#include "intel_vga.h"
#include "intel_vrr.h"
+#include "intel_vrr_regs.h"
#include "intel_wm.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
@@ -2638,6 +2639,27 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
PIPE_LINK_N2(display, transcoder));
}
+static void intel_crtc_set_vtotal(struct intel_display *display,
+ enum transcoder cpu_transcoder,
+ u32 crtc_vdisplay, u32 crtc_vtotal)
+{
+ u32 vtotal_bits;
+
+ /*
+ * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
+ * bits are not required. Since the support for these bits is going to
+ * be deprecated in upcoming platforms, avoid writing these bits for the
+ * platforms that do not use legacy Timing Generator.
+ */
+ if (intel_vrr_always_use_vrr_tg(display))
+ vtotal_bits = 0;
+ else
+ vtotal_bits = VTOTAL(crtc_vtotal - 1);
+
+ intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
+ VACTIVE(crtc_vdisplay - 1) | vtotal_bits);
+}
+
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@@ -2702,9 +2724,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
- intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
- VACTIVE(crtc_vdisplay - 1) |
- VTOTAL(crtc_vtotal - 1));
+ intel_crtc_set_vtotal(display, cpu_transcoder, crtc_vdisplay, crtc_vtotal);
+
intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
VBLANK_START(crtc_vblank_start - 1) |
VBLANK_END(crtc_vblank_end - 1));
@@ -2718,9 +2739,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
* bits. */
if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&
(pipe == PIPE_B || pipe == PIPE_C))
- intel_de_write(display, TRANS_VTOTAL(display, pipe),
- VACTIVE(crtc_vdisplay - 1) |
- VTOTAL(crtc_vtotal - 1));
+ intel_crtc_set_vtotal(display, (enum transcoder)pipe,
+ crtc_vdisplay, crtc_vtotal);
}
static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
@@ -2766,9 +2786,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
* The double buffer latch point for TRANS_VTOTAL
* is the transcoder's undelayed vblank.
*/
- intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
- VACTIVE(crtc_vdisplay - 1) |
- VTOTAL(crtc_vtotal - 1));
+ intel_crtc_set_vtotal(display, cpu_transcoder, crtc_vdisplay, crtc_vtotal);
intel_vrr_set_fixed_rr_timings(crtc_state);
intel_vrr_transcoder_enable(crtc_state);
@@ -2806,6 +2824,29 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
}
+static void intel_crtc_get_vtotal(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ u32 tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));
+
+ adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
+
+ /*
+ * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
+ * bits are not filled. Since for these platforms TRAN_VMIN is always
+ * filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for
+ * adjusted_mode.
+ */
+ if (intel_vrr_always_use_vrr_tg(display)) {
+ tmp = intel_de_read(display, TRANS_VRR_VMIN(display, cpu_transcoder));
+ adjusted_mode->crtc_vtotal = tmp + 1;
+ } else {
+ adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
+ }
+}
+
static void intel_get_transcoder_timings(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -2829,9 +2870,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
- tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));
- adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
- adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
+ intel_crtc_get_vtotal(pipe_config);
/* FIXME TGL+ DSI transcoders have this! */
if (!transcoder_is_dsi(cpu_transcoder)) {
@@ -8168,8 +8207,7 @@ void i830_enable_pipe(struct intel_display *display, enum pipe pipe)
HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
- intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
- VACTIVE(480 - 1) | VTOTAL(525 - 1));
+ intel_crtc_set_vtotal(display, cpu_transcoder, 480, 525);
intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
--
2.45.2
More information about the Intel-gfx-trybot
mailing list