[PATCH v5 17/17] just debug may 12
Mitul Golani
mitulkumar.ajitkumar.golani at intel.com
Tue May 13 04:48:48 UTC 2025
---
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 18 ++++-
drivers/gpu/drm/i915/display/intel_vrr.c | 66 +++++++++++++++++++
2 files changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 408037e3cf89..fe3530cfcede 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -175,7 +175,21 @@
#define _PIPEDMC_EVT_CTL_4_A 0x5f044
#define _PIPEDMC_EVT_CTL_4_B 0x5f444
-#define PIPEDMC_EVT_CTL_4(pipe) _MMIO_PIPE(pipe, _PIPEDMC_EVT_CTL_4_A,\
- _PIPEDMC_EVT_CTL_4_B)
+#define PIPEDMC_EVT_CTL_4(pipe) _MMIO_PIPE(pipe, _PIPEDMC_EVT_CTL_4_A, _PIPEDMC_EVT_CTL_4_B)
+
+#define _PIPEDMC_EVT_HTP_2_A 0x5F00C
+#define _PIPEDMC_EVT_HTP_2_B 0x5F40C
+#define PIPEDMC_EVT_HTP_2(pipe) _MMIO_PIPE(pipe, _PIPEDMC_EVT_HTP_2_A, _PIPEDMC_EVT_HTP_2_B)
+
+#define _PIPEDMC_EVT_HTP_3_A 0x5F010
+#define _PIPEDMC_EVT_HTP_3_B 0x5F410
+#define PIPEDMC_EVT_HTP_3(pipe) _MMIO_PIPE(pipe, _PIPEDMC_EVT_HTP_3_A, _PIPEDMC_EVT_HTP_3_B)
+
+#define _PIPEDMC_EVT_HTP_4_A 0x5F014
+#define _PIPEDMC_EVT_HTP_4_B 0x5F414
+#define PIPEDMC_EVT_HTP_4(pipe) _MMIO_PIPE(pipe, _PIPEDMC_EVT_HTP_4_A, _PIPEDMC_EVT_HTP_4_B)
+
+#define VTOTAL_PREV_MASK REG_GENMASK(19, 0)
+#define VTOTAL_PREV(vtotal) REG_FIELD_PREP(VTOTAL_PREV_MASK, (vtotal))
#endif /* __INTEL_DMC_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 25e8c76990d2..48864eb4408b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -548,6 +548,8 @@ void intel_vrr_send_push(struct intel_dsb *dsb,
{
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
if (!crtc_state->vrr.enable)
return;
@@ -555,6 +557,70 @@ void intel_vrr_send_push(struct intel_dsb *dsb,
if (dsb)
intel_dsb_nonpost_start(dsb);
+ if(DISPLAY_VER(display) >= 30) {
+ trace_printk("---------**DCB Regs**---------\n");
+ trace_printk("\n**PIPE_DMC Regs**\n");
+ trace_printk("EVT_CTL_2: %x, EVT_HTP_2: %x\n",
+ intel_de_read(display, PIPEDMC_EVT_CTL_2(pipe)),
+ intel_de_read(display, PIPEDMC_EVT_HTP_2(pipe)));
+ trace_printk("EVT_CTL_4: %x, EVT_HTP_4: %x\n",
+ intel_de_read(display, PIPEDMC_EVT_CTL_4(pipe)),
+ intel_de_read(display, PIPEDMC_EVT_HTP_4(pipe)));
+ trace_printk("EVT_CTL_3: %x EVT_HTP_3: %x PIPEDMC_DCB_CTL: %x\n",
+ intel_de_read(display, PIPEDMC_EVT_CTL_3(pipe)),
+ intel_de_read(display, PIPEDMC_EVT_HTP_3(pipe)),
+ intel_de_read(display, PIPEDMC_DCB_CTL(pipe)));
+ trace_printk("TRANS_VRR_CTL(60420): %x AS_DCB_CTL(604C0): %x\n",
+ intel_de_read(display, _MMIO(0x60420)),
+ intel_de_read(display, _MMIO(0x604C0)));
+ trace_printk("Version(90004): %x ALGO_RUN_STAGE(97E38): %x BALANCE(906E0): %d(d)\n",
+ intel_de_read(display, _MMIO(0x90004)),
+ intel_de_read(display, _MMIO(0x97E38)),
+ intel_de_read(display, _MMIO(0x906E0)));
+ trace_printk("DIRECTION(906E4): %d(d) TRANS_AS_DCB_ODD_COUNT(97EBC): %d(d) TRANS_AS_DCB_EVEN_COUNT(97EB8): %d(d)\n",
+ intel_de_read(display, _MMIO(0x906E4)),
+ intel_de_read(display, _MMIO(0x97EBC)),
+ intel_de_read(display, _MMIO(0x97EB8)));
+ trace_printk("PREDICTED_FRAMETIME(906D0): %d(d) FINAL_VTOTAL(97E68): %d(d) EARLIER_FLIPLINE(97E90): %d(d) EARLIER_FLIPLINE(97E64): %d(d)\n",
+ intel_de_read(display, _MMIO(0x906D0)),
+ intel_de_read(display, _MMIO(0x97E68)),
+ intel_de_read(display, _MMIO(0x97E90)),
+ intel_de_read(display, _MMIO(0x97E64)));
+ trace_printk("FINAL_FLIPLINE(97E60): %d(d) NUM_EARLY(97E5C): %d(d) MOD_BAL(97E58): %d(d) ADJUST(97E54): %d(d)\n",
+ intel_de_read(display, _MMIO(0x97E60)),
+ intel_de_read(display, _MMIO(0x97E5C)),
+ intel_de_read(display, _MMIO(0x97E58)),
+ intel_de_read(display, _MMIO(0x97E54)));
+ trace_printk("TRANS_LINKM1(60040): %x TRANS_LINKN1(60044): %x TRANS_HTOTAL(60000): %x TRANS_VRR_VTOTAL_PREV(60480): %d(d)\n",
+ intel_de_read(display, _MMIO(0x60040)),
+ intel_de_read(display, _MMIO(0x60044)),
+ HTOTAL(intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder))) >> 16,
+ intel_de_read(display, _MMIO(0x60480)));
+ trace_printk("FLIP_Count(70044): %d(d) FRAME_CNT(70040): %d(d) TRANS_ADAPTIVE_SYNC_DCB_ODD_COUNT_LIVE(604D0): %d(d) TRANS_ADAPTIVE_SYNC_DCB_EVEN_COUNT_LIVE(604CC): %d(d)\n",
+ intel_de_read(display, _MMIO(0x70044)),
+ intel_de_read(display, _MMIO(0x70040)),
+ intel_de_read(display, _MMIO(0x604D0)),
+ intel_de_read(display, _MMIO(0x604CC)));
+ trace_printk("PIPEDMC_HTP_RDBK(5F0BC): %x PIPEDMC_STATUS(5F06C): %x AS_DCB_CTL(604C0): %x\n",
+ intel_de_read(display, _MMIO(0x5F0BC)),
+ intel_de_read(display, _MMIO(0x5F06C)),
+ intel_de_read(display, _MMIO(0x604C0)));
+ trace_printk("TRANS_VRR_CTL(60420): %x TRANS_VRR_DCB_ADJ_VMAX_CFG(604D8): %d(d) TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(604D4): %d(d)\n",
+ intel_de_read(display, _MMIO(0x60420)),
+ intel_de_read(display, _MMIO(0x604D8)),
+ intel_de_read(display, _MMIO(0x604D4)));
+ trace_printk("TRANS_VRR_VMAX_DCB(60414): %d(d) TRANS_VRR_FLIPLINE(60438): %d(d) TRANS_VRR_FLIPLINE_DCB(60418): %d(d)\n",
+ intel_de_read(display, _MMIO(0x60414)),
+ intel_de_read(display, _MMIO(0x60438)),
+ intel_de_read(display, _MMIO(0x60418)));
+ trace_printk("FLIPLINE: %d(d) vmin: %d(d) vmax: %d(d) rr: %d(d))\n",
+ intel_de_read(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder)),
+ intel_de_read(display, TRANS_VRR_VMIN(display, cpu_transcoder)),
+ intel_de_read(display, TRANS_VRR_VMAX(display, cpu_transcoder)),
+ crtc_state->hw.adjusted_mode.clock*1000/(crtc_state->hw.adjusted_mode.htotal* (VTOTAL_PREV(intel_de_read(display, TRANS_VRR_VTOTAL_PREV(display, cpu_transcoder))) ? VTOTAL_PREV(intel_de_read(display, TRANS_VRR_VTOTAL_PREV(display, cpu_transcoder))): 1)));
+ trace_printk("\n------------------------------------------------------\n\n");
+ }
+
intel_de_write_dsb(display, dsb,
TRANS_PUSH(display, cpu_transcoder),
TRANS_PUSH_EN | TRANS_PUSH_SEND);
--
2.48.1
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