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<b>Patch Details</b>
<table>
<tr><td><b>Series:</b></td><td>series starting with [01/72] drm/i915: Use cmpxchg64 for 32b compatilibity</td></tr>
<tr><td><b>URL:</b></td><td><a href="https://patchwork.freedesktop.org/series/84860/">https://patchwork.freedesktop.org/series/84860/</a></td></tr>
<tr><td><b>State:</b></td><td>success</td></tr>
<tr><td><b>Details:</b></td><td><a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7308/index.html">https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7308/index.html</a></td></tr>
</table>
<h1>CI Bug Log - changes from CI_DRM_9478 -> Trybot_7308</h1>
<h2>Summary</h2>
<p><strong>SUCCESS</strong></p>
<p>No regressions found.</p>
<p>External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7308/index.html</p>
<h2>New tests</h2>
<p>New tests have been introduced between CI_DRM_9478 and Trybot_7308:</p>
<h3>New IGT tests (1)</h3>
<ul>
<li>igt@i915_selftest@live@scheduler:<ul>
<li>Statuses : 37 pass(s)</li>
<li>Exec time: [0.59, 9.50] s</li>
</ul>
</li>
</ul>
<h2>Known issues</h2>
<p>Here are the changes found in Trybot_7308 that come from known issues:</p>
<h3>IGT changes</h3>
<h4>Issues hit</h4>
<ul>
<li>igt@prime_vgem@basic-read:<ul>
<li>fi-tgl-y: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9478/fi-tgl-y/igt@prime_vgem@basic-read.html">PASS</a> -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7308/fi-tgl-y/igt@prime_vgem@basic-read.html">DMESG-WARN</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/402">i915#402</a>) +1 similar issue</li>
</ul>
</li>
</ul>
<h4>Possible fixes</h4>
<ul>
<li>igt@fbdev@read:<ul>
<li>fi-tgl-y: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9478/fi-tgl-y/igt@fbdev@read.html">DMESG-WARN</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/402">i915#402</a>) -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7308/fi-tgl-y/igt@fbdev@read.html">PASS</a> +1 similar issue</li>
</ul>
</li>
</ul>
<h2>Participating hosts (42 -> 40)</h2>
<p>Missing (2): fi-bdw-samus fi-hsw-4200u </p>
<h2>Build changes</h2>
<ul>
<li>Linux: CI_DRM_9478 -> Trybot_7308</li>
</ul>
<p>CI-20190529: 20190529<br />
CI_DRM_9478: 94cf3a4cc350324f21728c70954c46e535405c87 @ git://anongit.freedesktop.org/gfx-ci/linux<br />
IGT_5890: 0e209dc3cd7561a57ec45be74b8b299eaf391950 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools<br />
Trybot_7308: 0437629433438fbc695b7a6d1f6aef4d71ee9cd2 @ git://anongit.freedesktop.org/gfx-ci/linux</p>
<p>== Linux commits ==</p>
<p>043762943343 drm/i915/gt: Support virtual engine queues<br />
4ae2f14f2f96 active<br />
6a2a8918f54f drm/i915: Move saturated workload detection back to the context<br />
ca7231726d85 drm/i915/gt: Enable ring scheduling for gen6/7<br />
4348484d8809 drm/i915/gt: Implement ring scheduler for gen6/7<br />
0f420b09a022 drm/i915/gt: Enable busy-stats for ring-scheduler<br />
374ffa82e930 drm/i915/gt: Infrastructure for ring scheduling<br />
ba9b7e5b2b97 cl-g6<br />
2ea69544de3d drm/i915/gt: Use client timeline address for seqno writes<br />
edd5de9f030b drm/i915/gt: Support creation of 'internal' rings<br />
8481714ff4d6 drm/i915/gt: Couple tasklet scheduling for all CS interrupts<br />
f86990a30506 Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq"<br />
2442b3cd95ae drm/i915/gt: Another tweak for flushing the tasklets<br />
edd70bfa76f2 drm/i915: Move tasklet from execlists to sched<br />
4be75d274458 drm/i915: Move scheduler queue<br />
ed5e68bb14af drm/i915: Move common active lists from engine to i915_scheduler<br />
545ab06a67e9 drm/i915: Extend the priority boosting for the display with a deadline<br />
4fbb8b9c2371 drm/i915/gt: Specify a deadline for the heartbeat<br />
0352b72266c7 drm/i915: Fair low-latency scheduling<br />
14d36c15792e try_cmpxchg64<br />
2d196201ce60 drm/i915: Fix the iterative dfs for defering requests<br />
b29cdb426450 drm/i915: Extract the ability to defer and rerun a request later<br />
353bb31c1cc8 drm/i915: Extract request suspension from the execlists backend<br />
2b57d7de7842 drm/i915: Extract request submission from execlists<br />
e22e0372fc53 drm/i915/gt: Remove timeslice suppression<br />
4d6e33643766 drm/i915: Improve DFS for priority inheritance<br />
8e6d837bc5b3 drm/i915/selftests: Exercise priority inheritance around an engine loop<br />
154c4e1932f8 drm/i915/selftests: Measure set-priority duration<br />
ded311ac1967 drm/i915: Restructure priority inheritance<br />
65a3974f49ae drm/i915: Teach the i915_dependency to use a double-lock<br />
ef8b0f4f17ad drm/i915/gt: Do not suspend bonded requests if one hangs<br />
e1e5c448ff60 drm/i915: Replace engine->schedule() with a known request operation<br />
25e3c8d14c8a drm/i915: Prune empty priolists<br />
0ed71987d276 drm/i915/gt: Defer the kmem_cache_free() until after the HW submit<br />
be95c7542b78 drm/i915: Remove I915_USER_PRIORITY_SHIFT<br />
76ee38982220 drm/i915: Strip out internal priorities<br />
7286755cb2ff drm/i915/gt: Refactor heartbeat request construction and submission<br />
5587c4212d36 drm/i915/gt: Convert stats.active to plain unsigned int<br />
1700d24117d9 drm/i915/gt: Extract busy-stats for ring-scheduler<br />
7909162ff8b5 drm/i915/gt: Drop atomic for engine->fw_active tracking<br />
2b51b5dff3d7 drm/i915: Reduce test_and_set_bit to set_bit in i915_request_submit()<br />
25d61bcb99a1 drm/i915/gem: Reduce ctx->engines_mutex for get_engines()<br />
7ab00af4e966 drm/i915/gem: Reduce ctx->engine_mutex for reading the clone source<br />
b16ea0b6e6a4 drm/i915: Drop i915_request.lock requirement for intel_rps_boost()<br />
0175c8c0b37e drm/i915: Drop i915_request.lock serialisation around await_start<br />
3d646e6a3663 drm/i915/gem: Optimistically prune dma-resv from the shrinker.<br />
d9f64d85ac6c drm/i915/gt: Prefer recycling an idle fence<br />
90465901229f drm/i915/gt: Consolidate the CS timestamp clocks<br />
ec381d02597e drm/i915/display: Inject a failure into the initial modeset<br />
97ce07958bd4 drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock<br />
c9d78d460609 drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines<br />
52522731a518 drm/i915/selftests: Exercise relative timeline modes<br />
614a142bb76c drm/i915/gt: Use indices for writing into relative timelines<br />
b91978a30c25 drm/i915/gt: Add timeline "mode"<br />
277729fc1d1d drm/i915/gt: Track timeline GGTT offset separately from subpage offset<br />
f87844c7b990 drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb<br />
f38f205596c0 drm/i915/gt: Track all timelines created using the HWSP<br />
a844cc7d138e drm/i915: Encode fence specific waitqueue behaviour into the wait.flags<br />
be9164e2b0da drm/i915/gt: Track the overall awake/busy time<br />
6c104d84c98e drm/i915/gem: Drop free_work for GEM contexts<br />
5ce3b5ed3658 drm/i915/gt: ce->inflight updates are now serialised<br />
d8e32468ddf8 drm/i915/gt: Simplify virtual engine handling for execlists_hold()<br />
57d9e8bff51c resubmit-flush<br />
134a06844cad drm/i915/gt: Resubmit the virtual engine on schedule-out<br />
7767b5379037 drm/i915/gt: Shrink the critical section for irq signaling<br />
6c1085251ebb drm/i915/gt: Remove virtual breadcrumb before transfer<br />
e503b8e0ab15 drm/i915/gt: Defer schedule_out until after the next dequeue<br />
c5cf24628232 drm/i915/gt: Decouple inflight virtual engines<br />
7ad892df888a drm/i915/gt: Use virtual_engine during execlists_dequeue<br />
4adeec988913 drm/i915/gt: Replace direct submit with direct call to tasklet<br />
af2afdb87a9a drm/i915/uc: Squelch load failure error message<br />
84a29e3599d7 drm/i915: Use cmpxchg64 for 32b compatilibity</p>
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