<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8"/>
<title>Project List - Patchwork</title>
<style id="css-table-select" type="text/css">
td { padding: 2pt; }
</style>
</head>
<body>
<b>Patch Details</b>
<table>
<tr><td><b>Series:</b></td><td>series starting with [01/67] drm/i915/gt: Track all timelines created using the HWSP</td></tr>
<tr><td><b>URL:</b></td><td><a href="https://patchwork.freedesktop.org/series/85053/">https://patchwork.freedesktop.org/series/85053/</a></td></tr>
<tr><td><b>State:</b></td><td>failure</td></tr>
<tr><td><b>Details:</b></td><td><a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7337/index.html">https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7337/index.html</a></td></tr>
</table>
<h1>CI Bug Log - changes from CI_DRM_9501 -> Trybot_7337</h1>
<h2>Summary</h2>
<p><strong>FAILURE</strong></p>
<p>Serious unknown changes coming with Trybot_7337 absolutely need to be<br />
verified manually.</p>
<p>If you think the reported changes have nothing to do with the changes<br />
introduced in Trybot_7337, please notify your bug team to allow them<br />
to document this new failure mode, which will reduce false positives in CI.</p>
<p>External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7337/index.html</p>
<h2>Possible new issues</h2>
<p>Here are the unknown changes that may have been introduced in Trybot_7337:</p>
<h3>IGT changes</h3>
<h4>Possible regressions</h4>
<ul>
<li>
<p>igt@i915_selftest@live@gem_contexts:</p>
<ul>
<li>fi-bsw-nick: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9501/fi-bsw-nick/igt@i915_selftest@live@gem_contexts.html">PASS</a> -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7337/fi-bsw-nick/igt@i915_selftest@live@gem_contexts.html">INCOMPLETE</a></li>
</ul>
</li>
<li>
<p>igt@i915_selftest@live@gtt:</p>
<ul>
<li>fi-bsw-nick: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9501/fi-bsw-nick/igt@i915_selftest@live@gtt.html">PASS</a> -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7337/fi-bsw-nick/igt@i915_selftest@live@gtt.html">DMESG-WARN</a></li>
</ul>
</li>
</ul>
<h2>New tests</h2>
<p>New tests have been introduced between CI_DRM_9501 and Trybot_7337:</p>
<h3>New IGT tests (1)</h3>
<ul>
<li>igt@i915_selftest@live@scheduler:<ul>
<li>Statuses : 35 pass(s)</li>
<li>Exec time: [0.58, 9.42] s</li>
</ul>
</li>
</ul>
<h2>Known issues</h2>
<p>Here are the changes found in Trybot_7337 that come from known issues:</p>
<h3>IGT changes</h3>
<h4>Issues hit</h4>
<ul>
<li>
<p>igt@i915_pm_rpm@module-reload:</p>
<ul>
<li>fi-kbl-guc: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9501/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html">PASS</a> -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7337/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html">SKIP</a> (<a href="https://bugs.freedesktop.org/show_bug.cgi?id=109271">fdo#109271</a>)</li>
</ul>
</li>
<li>
<p>igt@i915_selftest@live@gt_heartbeat:</p>
<ul>
<li>fi-bsw-kefka: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9501/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html">PASS</a> -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7337/fi-bsw-kefka/igt@i915_selftest@live@gt_heartbeat.html">DMESG-FAIL</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/2675">i915#2675</a> / <a href="https://gitlab.freedesktop.org/drm/intel/issues/541">i915#541</a>)</li>
</ul>
</li>
<li>
<p>igt@prime_vgem@basic-fence-flip:</p>
<ul>
<li>fi-tgl-y: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9501/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html">PASS</a> -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7337/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html">DMESG-WARN</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/402">i915#402</a>) +1 similar issue</li>
</ul>
</li>
<li>
<p>igt@runner@aborted:</p>
<ul>
<li>fi-bsw-nick: NOTRUN -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7337/fi-bsw-nick/igt@runner@aborted.html">FAIL</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/1436">i915#1436</a> / <a href="https://gitlab.freedesktop.org/drm/intel/issues/2722">i915#2722</a> / <a href="https://gitlab.freedesktop.org/drm/intel/issues/483">i915#483</a>)</li>
</ul>
</li>
</ul>
<h4>Possible fixes</h4>
<ul>
<li>
<p>igt@gem_close_race@basic-threads:</p>
<ul>
<li>fi-tgl-y: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9501/fi-tgl-y/igt@gem_close_race@basic-threads.html">DMESG-WARN</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/402">i915#402</a>) -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7337/fi-tgl-y/igt@gem_close_race@basic-threads.html">PASS</a> +2 similar issues</li>
</ul>
</li>
<li>
<p>igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:</p>
<ul>
<li>fi-cfl-8109u: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9501/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html">DMESG-WARN</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/165">i915#165</a>) -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7337/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html">PASS</a> +15 similar issues</li>
</ul>
</li>
</ul>
<h2>Participating hosts (43 -> 38)</h2>
<p>Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan fi-bdw-samus </p>
<h2>Build changes</h2>
<ul>
<li>Linux: CI_DRM_9501 -> Trybot_7337</li>
</ul>
<p>CI-20190529: 20190529<br />
CI_DRM_9501: 65ea47daf580f4465a071d2e61ccff9b6c76dc53 @ git://anongit.freedesktop.org/gfx-ci/linux<br />
IGT_5908: b8b1391f7bfff83397ddc47c0083c2c7ed06be37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools<br />
Trybot_7337: 6e6dbaa2ea5087cfe907dee2bbbb3f6b1269a50f @ git://anongit.freedesktop.org/gfx-ci/linux</p>
<p>== Linux commits ==</p>
<p>6e6dbaa2ea50 drm/i915: Bump default timeslicing quantum to 5ms<br />
7ab0c911b429 drm/i915: Move saturated workload detection back to the context<br />
8376ee084f27 drm/i915/gt: Support virtual engine queues<br />
e242bb555646 drm/i915/gt: Skip over completed active execlists, again<br />
3f0fcffed71a drm/i915/gt: Enable ring scheduling for gen6/7<br />
0a2493c0508c drm/i915/gt: Implement ring scheduler for gen6/7<br />
f269fa149910 drm/i915/gt: Enable busy-stats for ring-scheduler<br />
c2c1b1a50b84 drm/i915/gt: Infrastructure for ring scheduling<br />
4f92be31431b drm/i915/gt: Use client timeline address for seqno writes<br />
70411192a299 drm/i915/gt: Support creation of 'internal' rings<br />
b9d95439af91 drm/i915/gt: Couple tasklet scheduling for all CS interrupts<br />
b73a2b567b98 Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq"<br />
13bd858f6f67 drm/i915/gt: Another tweak for flushing the tasklets<br />
09946e59b7f5 drm/i915: Move tasklet from execlists to sched<br />
bb229654603a drm/i915: Move scheduler queue<br />
b2260e61e59b drm/i915: Move common active lists from engine to i915_scheduler<br />
60f6e5dcd9b1 drm/i915: Extend the priority boosting for the display with a deadline<br />
2eb8d4070013 drm/i915/gt: Specify a deadline for the heartbeat<br />
ca97a304f1dc drm/i915: Fair low-latency scheduling<br />
df8a3766ab43 drm/i915: Wrap cmpxchg64 with try_cmpxchg64() helper<br />
592821d95e21 drm/i915: Fix the iterative dfs for defering requests<br />
0fb2d0bae7d8 drm/i915: Extract the ability to defer and rerun a request later<br />
b8cb188dcf35 drm/i915: Extract request suspension from the execlists backend<br />
da975cfd4271 drm/i915: Extract request submission from execlists<br />
0dd9e9ab3532 drm/i915/gt: Remove timeslice suppression<br />
6cb009056d67 drm/i915: Improve DFS for priority inheritance<br />
9f00c8874478 drm/i915/selftests: Exercise priority inheritance around an engine loop<br />
37d4c9b18ce0 drm/i915/selftests: Measure set-priority duration<br />
94992365b4a8 drm/i915: Restructure priority inheritance<br />
9bcb2e26627c drm/i915: Teach the i915_dependency to use a double-lock<br />
9e6178fdfdb0 drm/i915/gt: Do not suspend bonded requests if one hangs<br />
6a8aa3d84310 drm/i915: Replace engine->schedule() with a known request operation<br />
ca9637222ab4 drm/i915: Prune empty priolists<br />
b39f1a769b95 drm/i915/gt: Defer the kmem_cache_free() until after the HW submit<br />
79709149aa67 drm/i915: Remove I915_USER_PRIORITY_SHIFT<br />
cd952932f715 drm/i915: Strip out internal priorities<br />
ef43926065d9 drm/i915/gt: Refactor heartbeat request construction and submission<br />
30d269668193 drm/i915/gt: Convert stats.active to plain unsigned int<br />
c3dd0c0f26e6 drm/i915/gt: Extract busy-stats for ring-scheduler<br />
9d6342afd038 drm/i915/gt: Drop atomic for engine->fw_active tracking<br />
dd74f2ad276a drm/i915: Reduce test_and_set_bit to set_bit in i915_request_submit()<br />
f9570b774dfb drm/i915/gem: Reduce ctx->engines_mutex for get_engines()<br />
b29612b87d0f drm/i915/gem: Reduce ctx->engine_mutex for reading the clone source<br />
21df3c279450 drm/i915: Drop i915_request.lock requirement for intel_rps_boost()<br />
2506a1737ebe drm/i915: Drop i915_request.lock serialisation around await_start<br />
e0d04b8c0f74 drm/i915/gem: Optimistically prune dma-resv from the shrinker.<br />
bf5904e6d014 drm/i915/gt: Prefer recycling an idle fence<br />
e551788322f8 drm/i915/gt: Consolidate the CS timestamp clocks<br />
f3c90fb290a3 drm/i915/selftests: Confirm RING_TIMESTAMP / CTX_TIMESTAMP share a clock<br />
437b0d6858b8 drm/i915/gt: ce->inflight updates are now serialised<br />
07b941ed9a91 drm/i915/gt: Simplify virtual engine handling for execlists_hold()<br />
9c1961dc0e6e drm/i915/gt: Resubmit the virtual engine on schedule-out<br />
8513c7ee9d91 drm/i915/gt: Shrink the critical section for irq signaling<br />
c2894d06d3fe drm/i915/gt: Remove virtual breadcrumb before transfer<br />
9d5c10fad5e6 drm/i915/gt: Defer schedule_out until after the next dequeue<br />
33ee58f590d8 drm/i915/gt: Decouple inflight virtual engines<br />
1ae8140a8353 drm/i915/gt: Use virtual_engine during execlists_dequeue<br />
022a50dfbc45 drm/i915/gt: Replace direct submit with direct call to tasklet<br />
ae748fecde77 drm/i915/uc: Squelch load failure error message<br />
68903f6fadbd drm/i915: Use cmpxchg64 for 32b compatilibity<br />
d8f201cddd34 drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines<br />
34eb6f9d8618 drm/i915/selftests: Exercise relative timeline modes<br />
e93eb8c95b8d drm/i915/gt: Use indices for writing into relative timelines<br />
ad77313aa905 drm/i915/gt: Add timeline "mode"<br />
cb87c2949e0b drm/i915/gt: Track timeline GGTT offset separately from subpage offset<br />
69dcee6add09 drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb<br />
54ba3310c8b2 drm/i915/gt: Track all timelines created using the HWSP</p>
</body>
</html>