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<b>Patch Details</b>
<table>
<tr><td><b>Series:</b></td><td>series starting with [01/63] drm/i915/gt: Restrict the GT clock override to just Icelake</td></tr>
<tr><td><b>URL:</b></td><td><a href="https://patchwork.freedesktop.org/series/86502/">https://patchwork.freedesktop.org/series/86502/</a></td></tr>
<tr><td><b>State:</b></td><td>failure</td></tr>
<tr><td><b>Details:</b></td><td><a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7522/index.html">https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7522/index.html</a></td></tr>
</table>
<h1>CI Bug Log - changes from CI_DRM_9707 -> Trybot_7522</h1>
<h2>Summary</h2>
<p><strong>FAILURE</strong></p>
<p>Serious unknown changes coming with Trybot_7522 absolutely need to be<br />
verified manually.</p>
<p>If you think the reported changes have nothing to do with the changes<br />
introduced in Trybot_7522, please notify your bug team to allow them<br />
to document this new failure mode, which will reduce false positives in CI.</p>
<p>External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7522/index.html</p>
<h2>Possible new issues</h2>
<p>Here are the unknown changes that may have been introduced in Trybot_7522:</p>
<h3>IGT changes</h3>
<h4>Possible regressions</h4>
<ul>
<li>igt@kms_chamelium@common-hpd-after-suspend:<ul>
<li>fi-icl-u2: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9707/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html">PASS</a> -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7522/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html">DMESG-WARN</a></li>
</ul>
</li>
</ul>
<h2>New tests</h2>
<p>New tests have been introduced between CI_DRM_9707 and Trybot_7522:</p>
<h3>New IGT tests (1)</h3>
<ul>
<li>igt@i915_selftest@live@scheduler:<ul>
<li>Statuses : 35 pass(s)</li>
<li>Exec time: [0.68, 10.01] s</li>
</ul>
</li>
</ul>
<h2>Known issues</h2>
<p>Here are the changes found in Trybot_7522 that come from known issues:</p>
<h3>IGT changes</h3>
<h4>Issues hit</h4>
<ul>
<li>
<p>igt@i915_selftest@live@late_gt_pm:</p>
<ul>
<li>fi-bsw-n3050: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9707/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html">PASS</a> -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7522/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html">DMESG-FAIL</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/2927">i915#2927</a>)</li>
</ul>
</li>
<li>
<p>igt@prime_self_import@basic-with_two_bos:</p>
<ul>
<li>fi-tgl-y: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9707/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html">PASS</a> -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7522/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html">DMESG-WARN</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/402">i915#402</a>) +1 similar issue</li>
</ul>
</li>
<li>
<p>igt@runner@aborted:</p>
<ul>
<li>fi-bsw-n3050: NOTRUN -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7522/fi-bsw-n3050/igt@runner@aborted.html">FAIL</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/1436">i915#1436</a>)</li>
</ul>
</li>
</ul>
<h4>Possible fixes</h4>
<ul>
<li>
<p>igt@i915_selftest@live@gt_heartbeat:</p>
<ul>
<li>{fi-tgl-dsi}: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9707/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html">DMESG-FAIL</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/2601">i915#2601</a>) -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7522/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html">PASS</a></li>
</ul>
</li>
<li>
<p>igt@prime_self_import@basic-with_one_bo_two_files:</p>
<ul>
<li>fi-tgl-y: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9707/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html">DMESG-WARN</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/402">i915#402</a>) -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7522/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html">PASS</a> +1 similar issue</li>
</ul>
</li>
</ul>
<p>{name}: This element is suppressed. This means it is ignored when computing<br />
the status of the difference (SUCCESS, WARNING, or FAILURE).</p>
<h2>Participating hosts (44 -> 39)</h2>
<p>Missing (5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus </p>
<h2>Build changes</h2>
<ul>
<li>Linux: CI_DRM_9707 -> Trybot_7522</li>
</ul>
<p>CI-20190529: 20190529<br />
CI_DRM_9707: 062ea009eeff972b43c0de7eab0dee9923971257 @ git://anongit.freedesktop.org/gfx-ci/linux<br />
IGT_5980: e02612921a4e95aef3a368e7468f4337c9dcee7d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools<br />
Trybot_7522: 9995f49ab1127ac2ab8cfecf76dd5419776f4754 @ git://anongit.freedesktop.org/gfx-ci/linux</p>
<p>== Linux commits ==</p>
<p>9995f49ab112 ce-breadcrumbs<br />
03b75bab35dd submit-engine<br />
f2124d4b48a7 pass-engine-to-bb_start<br />
ff603dba4097 pass-engine-to-flush<br />
c192396e3f41 pass-engine-to-breadcrumb<br />
97312481eb40 cops-request-init<br />
389c72fb2935 drm/i915/gt: Limit C-states while waiting for requests<br />
5dab2cf748fa drm/i915: Support secure dispatch on gen6/gen7<br />
717f98a3633a drm/i915/gt: Enable ring scheduling for gen5-7<br />
2d619af5c3b2 drm/i915/gt: Implement ring scheduler for gen4-7<br />
7db1cdfd8943 drm/i915/gt: Infrastructure for ring scheduling<br />
df45dcadd3b0 drm/i915/gt: Use client timeline address for seqno writes<br />
b354774af4ee drm/i915/gt: Support creation of 'internal' rings<br />
012769cc968b drm/i915/gt: Couple tasklet scheduling for all CS interrupts<br />
364503b7182f Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq"<br />
bc0a310c0830 drm/i915/gt: Use ppHWSP for unshared non-semaphore related timelines<br />
dc7ec216bd13 drm/i915/selftests: Exercise relative timeline modes<br />
1c84f3d9d3e1 drm/i915/gt: Use indices for writing into relative timelines<br />
9111e5dc29a1 drm/i915/gt: Add timeline "mode"<br />
da8aea5f5389 drm/i915/gt: Track timeline GGTT offset separately from subpage offset<br />
a28c4561e821 drm/i915/gt: Wrap intel_timeline.has_initial_breadcrumb<br />
627a9e39c898 drm/i915/gt: Delay taking irqoff for execlists submission<br />
4d148d9b990e drm/i915: Bump default timeslicing quantum to 5ms<br />
2b3c6944685a drm/i915: Move saturated workload detection back to the context<br />
c02b5f7bb320 drm/i915/gt: Support virtual engine queues<br />
f70dd774a01e drm/i915: Extend the priority boosting for the display with a deadline<br />
72b6659d97d4 drm/i915/gt: Specify a deadline for the heartbeat<br />
42d090090d8f drm/i915: Fair low-latency scheduling<br />
392f99209b3c drm/i915: Wrap cmpxchg64 with try_cmpxchg64() helper<br />
030eac95067f drm/i915: Replace priolist rbtree with a skiplist<br />
f916a3694b06 drm/i915: Move preempt-reset flag to the scheduler<br />
a71813ecde0f drm/i915: Move busywaiting control to the scheduler<br />
285b21889cba drm/i915: Move needs-breadcrumb flags to scheduler<br />
2e170655cb8e drm/i915/gt: Declare when we enabled timeslicing<br />
337c54565823 drm/i915: Move timeslicing flag to scheduler<br />
13822f216edd drm/i915: Move scheduler flags<br />
3b376410bf80 drm/i915: Wrap i915_request_use_semaphores()<br />
3a3eacd10005 drm/i915: Show execlists queues when dumping state<br />
ccc369f58f6f drm/i915: Move finding the current active request to the scheduler<br />
d4ffb8d86e64 drm/i915: Move submit_request to i915_sched_engine<br />
d5c8604cf175 drm/i915/gt: Only kick the scheduler on timeslice/preemotin changing<br />
77cedc6d6df3 drm/i915: Move scheduler queue<br />
c34cce5671a2 drm/i915: Move common active lists from engine to i915_scheduler<br />
42009e00be43 drm/i915: Wrap access to intel_engine.active<br />
ea5bc142da08 drm/i915: Fix the iterative dfs for defering requests<br />
1188993d0612 drm/i915: Extract the ability to defer and rerun a request later<br />
d4efa14178be drm/i915: Extract request suspension from the execlists<br />
324c651ce9ac drm/i915: Extract request rewinding from execlists<br />
391756447e07 drm/i915: Extract request submission from execlists<br />
60eac05512ba drm/i915: Improve DFS for priority inheritance<br />
2233b5a28c09 drm/i915/selftests: Force a rewind if at first we don't succeed<br />
12ead1092e3e drm/i915/selftests: Exercise priority inheritance around an engine loop<br />
6c0f90ab1078 drm/i915/selftests: Measure set-priority duration<br />
23005b22b1c8 drm/i915: Restructure priority inheritance<br />
8a1aa46823ef drm/i915: Replace engine->schedule() with a known request operation<br />
73ccd1dd3484 drm/i915/gt: Move submission_method into intel_gt<br />
30bb69a997ec drm/i915/gt: Move engine setup out of set_default_submission<br />
f4c7eefbc4f3 drm/i915/gt: Always flush the submission queue on checking for idle<br />
30d89d6a82c1 drm/i915: Take rcu_read_lock for querying fence's driver/timeline names<br />
f68ec9a2a316 drm/i915: Protect against request freeing during cancellation on wedging<br />
d07687055963 drm/i915/selftests: Exercise cross-process context isolation<br />
27b07a02a104 drm/i915/selftests: Exercise relative mmio paths to non-privileged registers<br />
07e307c5ac79 drm/i915/gt: Restrict the GT clock override to just Icelake</p>
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