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<b>Patch Details</b>
<table>
<tr><td><b>Series:</b></td><td>drm/i915/mtl: Add C10 and C20 phy support (rev2)</td></tr>
<tr><td><b>URL:</b></td><td><a href="https://patchwork.freedesktop.org/series/115555/">https://patchwork.freedesktop.org/series/115555/</a></td></tr>
<tr><td><b>State:</b></td><td>success</td></tr>
<tr><td><b>Details:</b></td><td><a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_115555v2/index.html">https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_115555v2/index.html</a></td></tr>
</table>
<h1>CI Bug Log - changes from CI_DRM_12909 -> Trybot_115555v2</h1>
<h2>Summary</h2>
<p><strong>SUCCESS</strong></p>
<p>No regressions found.</p>
<p>External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_115555v2/index.html</p>
<h2>Participating hosts (37 -> 36)</h2>
<p>Missing (1): fi-snb-2520m </p>
<h2>Known issues</h2>
<p>Here are the changes found in Trybot_115555v2 that come from known issues:</p>
<h3>IGT changes</h3>
<h4>Issues hit</h4>
<ul>
<li>
<p>igt@i915_suspend@basic-s3-without-i915:</p>
<ul>
<li>bat-rpls-2: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12909/bat-rpls-2/igt@i915_suspend@basic-s3-without-i915.html">PASS</a> -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_115555v2/bat-rpls-2/igt@i915_suspend@basic-s3-without-i915.html">ABORT</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/6687">i915#6687</a> / <a href="https://gitlab.freedesktop.org/drm/intel/issues/7978">i915#7978</a>)</li>
</ul>
</li>
<li>
<p>igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:</p>
<ul>
<li>bat-dg2-11: NOTRUN -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_115555v2/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html">SKIP</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/5354">i915#5354</a>)</li>
</ul>
</li>
<li>
<p>igt@kms_pipe_crc_basic@read-crc:</p>
<ul>
<li>bat-adlp-9: NOTRUN -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_115555v2/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc.html">SKIP</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/3546">i915#3546</a>) +1 similar issue</li>
</ul>
</li>
</ul>
<h4>Possible fixes</h4>
<ul>
<li>igt@i915_selftest@live@gt_heartbeat:<ul>
<li>fi-cfl-guc: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12909/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html">DMESG-FAIL</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/5334">i915#5334</a>) -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_115555v2/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html">PASS</a></li>
</ul>
</li>
</ul>
<h4>Warnings</h4>
<ul>
<li>igt@i915_selftest@live@slpc:<ul>
<li>bat-rpls-1: <a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12909/bat-rpls-1/igt@i915_selftest@live@slpc.html">DMESG-FAIL</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/6367">i915#6367</a>) -> <a href="https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_115555v2/bat-rpls-1/igt@i915_selftest@live@slpc.html">DMESG-FAIL</a> (<a href="https://gitlab.freedesktop.org/drm/intel/issues/6367">i915#6367</a> / <a href="https://gitlab.freedesktop.org/drm/intel/issues/7996">i915#7996</a>)</li>
</ul>
</li>
</ul>
<h2>Build changes</h2>
<ul>
<li>Linux: CI_DRM_12909 -> Trybot_115555v2</li>
</ul>
<p>CI-20190529: 20190529<br />
CI_DRM_12909: 570255a5f5def30955477836cf87b00e587638d0 @ git://anongit.freedesktop.org/gfx-ci/linux<br />
IGT_7216: 0682c2b07c7eab2bf384899c3da3cc7f08083847 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git<br />
Trybot_115555v2: 570255a5f5def30955477836cf87b00e587638d0 @ git://anongit.freedesktop.org/gfx-ci/linux</p>
<h3>Linux commits</h3>
<p>107d64b80932 drm/i915/mtl: Pin assignment for TypeC<br />
fd13056b7f5f drm/i915/mtl: TypeC HPD live status query<br />
0370e36e9012 drm/i915/mtl: Power up TCSS<br />
6efc45c8db82 drm/i915/mtl: Define mask for DDI AUX interrupts<br />
1f4345f0752b drm/i915/mtl: MTL PICA hotplug detection<br />
351ccf67cae6 drm/i915/mtl: Enable TC ports<br />
9ece7a6d0256 drm/i915/mtl: Readout Thunderbolt HW state<br />
44a7839ab5b7 drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll<br />
da97b642d1d0 drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA<br />
5f872da3f352 drm/i915/mtl: Add voltage swing sequence for C20<br />
81af3f261b31 drm/i915/mtl: C20 port clock calculation<br />
96fb2fd78a76 drm/i915/mtl: Dump C20 pll hw state<br />
504cf0cd1555 drm/i915/mtl: C20 HW readout<br />
46d787e4df16 drm/i915/mtl: C20 PLL programming<br />
9a2cadab40b4 drm/i915/mtl: Add support for PM DEMAND<br />
05c7d316dbad drm/i915/mtl: Add vswing programming for C10 phys<br />
0a495c19fa6a drm/i915/mtl: Add C10 phy programming for HDMI<br />
73b07902f88f drm/i915/mtl: Add Support for C10 PHY message bus and pll programming<br />
779d4fe72cf2 drm/i915/mtl: Create separate reg file for PICA registers<br />
ab9275a9cad3 drm/i915/mtl: Add DP rates<br />
285bb0106938 drm/i915/mtl: Initial DDI port setup<br />
fbfea5d8e1bf x86/topology: fix erroneous smp_num_siblings on Intel Hybrid platform</p>
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