[Intel-gfx] [PATCH] intel: Cache tiling/swizzle state in user mode. Reset tiling on reuse.
Eric Anholt
eric at anholt.net
Tue Dec 16 02:38:59 CET 2008
On Mon, 2008-12-15 at 15:08 -0800, Keith Packard wrote:
> Remember tiling mode values provided by appplications, and
> record tiling mode when creating a buffer from another application. This
> eliminates any need to ask the kernel for tiling values and also makes
> reused buffers get the right tiling.
This looks better than my version of the same patch.
> Signed-off-by: Keith Packard <keithp at keithp.com>
> ---
> libdrm/intel/intel_bufmgr_gem.c | 65 +++++++++++++++++++++++++++-----------
> 1 files changed, 46 insertions(+), 19 deletions(-)
>
> diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c
> index 4a1b2f3..323007a 100644
> --- a/libdrm/intel/intel_bufmgr_gem.c
> +++ b/libdrm/intel/intel_bufmgr_gem.c
> @@ -128,6 +128,12 @@ struct _drm_intel_bo_gem {
> */
> int swrast;
>
> + /**
> + * Current tiling mode
> + */
> + uint32_t tiling_mode;
> + uint32_t swizzle_mode;
> +
> /** Array passed to the DRM containing relocation information. */
> struct drm_i915_gem_relocation_entry *relocs;
> /** Array of bos corresponding to relocs[i].target_handle */
> @@ -171,6 +177,17 @@ static unsigned int
> drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count);
>
> static int
> +drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
> + uint32_t *swizzle_mode);
> +
> +static int
> +drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
> + uint32_t stride);
> +
> +static void
> +drm_intel_gem_bo_unreference(drm_intel_bo *bo);
> +
> +static int
> logbase2(int n)
> {
> int i = 1;
> @@ -370,6 +387,8 @@ drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
> bo_gem->validate_index = -1;
> bo_gem->reloc_tree_size = bo_gem->bo.size;
> bo_gem->used_as_reloc_target = 0;
> + bo_gem->tiling_mode = I915_TILING_NONE;
> + bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
>
> DBG("bo_create: buf %d (%s) %ldb\n",
> bo_gem->gem_handle, bo_gem->name, size);
> @@ -391,6 +410,7 @@ drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, const char *name,
> drm_intel_bo_gem *bo_gem;
> int ret;
> struct drm_gem_open open_arg;
> + struct drm_i915_gem_get_tiling get_tiling;
>
> bo_gem = calloc(1, sizeof(*bo_gem));
> if (!bo_gem)
> @@ -414,6 +434,15 @@ drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, const char *name,
> bo_gem->validate_index = -1;
> bo_gem->gem_handle = open_arg.handle;
> bo_gem->global_name = handle;
> +
> + get_tiling.handle = bo_gem->gem_handle;
> + ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
> + if (ret != 0) {
> + drm_intel_gem_bo_unreference(&bo_gem->bo);
> + return NULL;
> + }
> + bo_gem->tiling_mode = get_tiling.tiling_mode;
> + bo_gem->swizzle_mode = get_tiling.swizzle_mode;
>
> DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
>
> @@ -466,6 +495,7 @@ drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo)
> {
> drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
> drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
> + uint32_t tiling_mode;
>
> if (--bo_gem->refcount == 0) {
> struct drm_intel_gem_bo_bucket *bucket;
> @@ -483,12 +513,16 @@ drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo)
> DBG("bo_unreference final: %d (%s)\n",
> bo_gem->gem_handle, bo_gem->name);
>
> - bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
> + bucket = NULL;
> + if (bo_gem->global_name == 0)
> + bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
> /* Put the buffer into our internal cache for reuse if we can. */
> - if (bucket != NULL &&
> + tiling_mode = I915_TILING_NONE;
> + if (bucket != NULL &&
> (bucket->max_entries == -1 ||
> (bucket->max_entries > 0 &&
> - bucket->num_entries < bucket->max_entries)))
> + bucket->num_entries < bucket->max_entries)) &&
> + drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0)
> {
> bo_gem->name = 0;
> bo_gem->validate_index = -1;
> @@ -1013,17 +1047,22 @@ drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
> struct drm_i915_gem_set_tiling set_tiling;
> int ret;
>
> + if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
> + return 0;
> +
> set_tiling.handle = bo_gem->gem_handle;
> set_tiling.tiling_mode = *tiling_mode;
> set_tiling.stride = stride;
>
> ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
> if (ret != 0) {
> - *tiling_mode = I915_TILING_NONE;
> + *tiling_mode = bo_gem->tiling_mode;
> return -errno;
> }
> + bo_gem->tiling_mode = set_tiling.tiling_mode;
> + bo_gem->swizzle_mode = set_tiling.swizzle_mode;
>
> - *tiling_mode = set_tiling.tiling_mode;
> + *tiling_mode = bo_gem->tiling_mode;
> return 0;
> }
>
> @@ -1031,22 +1070,10 @@ static int
> drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
> uint32_t *swizzle_mode)
> {
> - drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
> drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
> - struct drm_i915_gem_get_tiling get_tiling;
> - int ret;
> -
> - get_tiling.handle = bo_gem->gem_handle;
> -
> - ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
> - if (ret != 0) {
> - *tiling_mode = I915_TILING_NONE;
> - *swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
> - return -errno;
> - }
>
> - *tiling_mode = get_tiling.tiling_mode;
> - *swizzle_mode = get_tiling.swizzle_mode;
> + *tiling_mode = bo_gem->tiling_mode;
> + *swizzle_mode = bo_gem->swizzle_mode;
> return 0;
> }
>
--
Eric Anholt
eric at anholt.net eric.anholt at intel.com
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