[Intel-gfx] [PATCH] gpu/drm/i915: MSI needs IRM set before any other registers are touched.

[Keith Packard]

If the mask register is not set on ISR entry, eventually the chip will stop
delivering interrupts. This patch also avoids reading the pipe status
registers on each interrupt.

Signed-off-by: Keith Packard <keithp at keithp.com>
---

This gets interrupts working for me on 965GM. This is just the MSI and
pipestat changes, without the vblank changes I included in my previous
patch. Not that vblank is working on 965GM, but it wasn't working with
my changes either. Can we abandon vblank until DRI2 saves us all?

 drivers/gpu/drm/i915/i915_irq.c |   15 +++++++++------
 1 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d47805a..5888158 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -271,12 +271,9 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 {
 	struct drm_device *dev = (struct drm_device *) arg;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	u32 pipea_stats, pipeb_stats;
+	u32 pipea_stats = 0, pipeb_stats = 0;
 	u32 iir;
 
-	pipea_stats = I915_READ(PIPEASTAT);
-	pipeb_stats = I915_READ(PIPEBSTAT);
-
 	if (dev->pdev->msi_enabled)
 		I915_WRITE(IMR, ~0);
 	iir = I915_READ(IIR);
@@ -291,8 +288,14 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 		return IRQ_NONE;
 	}
 
-	I915_WRITE(PIPEASTAT, pipea_stats);
-	I915_WRITE(PIPEBSTAT, pipeb_stats);
+	if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
+		pipea_stats = I915_READ(PIPEASTAT);
+		I915_WRITE(PIPEASTAT, pipea_stats);
+	}
+	if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
+		pipeb_stats = I915_READ(PIPEBSTAT);
+		I915_WRITE(PIPEBSTAT, pipeb_stats);
+	}
 
 	I915_WRITE(IIR, iir);
 	if (dev->pdev->msi_enabled)
-- 
1.5.6.5
-- 
keith.packard at intel.com
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