[Intel-gfx] [PATCH 1/2] drm/i915: Use the software DRRS to select the alternative frequency for LVDS

[Eric Anholt]

On Thu, 5 Nov 2009 08:26:53 -0800, Jesse Barnes <jbarnes at virtuousgeek.org> wrote:
> On Thu,  5 Nov 2009 11:27:16 +0800
> yakui.zhao at intel.com wrote:
> 
> > @@ -3047,20 +3047,20 @@ static int intel_crtc_mode_set(struct
> > drm_crtc *crtc, udelay(150);
> >  	}
> >  
> > +	/*
> > +	 * According to the spec We can select between two
> > alternative
> > +	 * frequency by using DRRS bit only when the CxSR bit in
> > PIPECONF
> > +	 * register is zero. So it will clear the CxSR bit of
> > PIPECONF
> > +	 * register.
> > +	 */
> >  	if (is_lvds && has_reduced_clock && i915_powersave) {
> >  		I915_WRITE(fp_reg + 4, fp2);
> >  		intel_crtc->lowfreq_avail = true;
> > -		if (HAS_PIPE_CXSR(dev)) {
> > -			DRM_DEBUG_KMS("enabling CxSR
> > downclocking\n");
> > -			pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
> > -		}
> > +		pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
> >  	} else {
> >  		I915_WRITE(fp_reg + 4, fp);
> >  		intel_crtc->lowfreq_avail = false;
> > -		if (HAS_PIPE_CXSR(dev)) {
> > -			DRM_DEBUG_KMS("disabling CxSR
> > downclocking\n");
> > -			pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
> > -		}
> > +		pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
> >  	}
> >  
> >  	I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
> > @@ -3750,7 +3750,7 @@ static void intel_increase_pllclock(struct
> > drm_crtc *crtc, bool schedule) if (!dev_priv->lvds_downclock_avail)
> >  		return;
> >  
> > -	if (!HAS_PIPE_CXSR(dev) && (dpll &
> > DISPLAY_RATE_SELECT_FPA1)) {
> > +	if (HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1))
> > { DRM_DEBUG_DRIVER("upclocking LVDS\n");
> 
> Don't we want to use the automatic C-state based downclock if
> possible?  That's the idea behind the manual clocking (in
> increase/decrease_pllclock) and the automatic clocking bit in the
> pipeconf register at least.  Did you test that and find it to be buggy
> or something?

Any response?