[Intel-gfx] [PATCH v2] drm/i915: enable memory self refresh on 945

[Peng Li]

> On Wed, 09 Dec 2009 13:25:39 +0800
> Li Peng <peng.li at linux.intel.com> wrote:
>
>> I did some test and found that memory self refresh on 945
>> isn't really enabled in commit 652c39. On 945, we need to use
>> bit 31 of FW_BLC_SELF to enable the write to self refresh bit
>> and bit 16 to enable the write of self refresh watermark, and
>> memory self refresh will take effect when CPU enters C3+ state.
>>
>> This patch enables memory self refresh on 945 when graphics
>> is idle, and disable self refresh when it is busy. In my test
>> on a netbook of 945GSE chipset, it saves about 0.8W idle power.
>>
>> Signed-off-by: Li Peng <peng.li at intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h      |    4 +++-
>>  drivers/gpu/drm/i915/intel_display.c |   23 ++++++++++++++++++++++-
>>  2 files changed, 25 insertions(+), 2 deletions(-)
>
> I'd like to figure out why I don't see hangs on my AspireOne without
> the idle/busy change you have here, since SR should be totally
> automatic afaik. Also, we may as well include the i915 path as well
> (after testing some more of course), since it affects this same code
> path.
>
OK, Please see https://bugs.freedesktop.org/show_bug.cgi?id=25553
for more info about this issue.
> --
> Jesse Barnes, Intel Open Source Technology Center
>