[Intel-gfx] [PATCH] Disable DRI2 buffer tiling on non-965, as those need fence regs for 2D blits.

[Eric Anholt]

This fixes glReadPixels failure on single-channel 915GM, as the software code
for readpixels was actually the only code in the driver doing tiling against
these buffers (everything else says "rely on fence registers", since the 2D
blits don't have a "don't rely on fence registers" option).
---
 src/i830_dri.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/src/i830_dri.c b/src/i830_dri.c
index 0fe0eca..c4440ce 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -1883,6 +1883,15 @@ I830DRI2CreateBuffers(DrawablePtr pDraw, unsigned int *attachments, int count)
 		break;
 	    }
 
+	    /* Disable tiling on 915-class 3D for now.  Because the 2D blitter
+	     * requires fence regs to operate, and they're not being managed
+	     * by the kernel yet, we don't want to expose tiled buffers to the
+	     * 3D client as it'll just render incorrectly if it pays attention
+	     * to our tiling bits at all.
+	     */
+	    if (!IS_I965G(pI830))
+		tiling = I915_TILING_NONE;
+
 	    if (tiling != I915_TILING_NONE) {
 		bo = i830_get_pixmap_bo(pPixmap);
 		drm_intel_bo_set_tiling(bo, &tiling,
-- 
1.5.6.5