[Intel-gfx] [RFC] support tiled rendering on pre-965 chips

[Jesse Barnes]

With DRI2 and UXA we don't actually tile back, depth or fake front buffers 
like we should on pre-965 chips, since they require fence regs to be set up 
in order to render properly.

This patchset re-adds basic support for tiled rendering on pre-965 in some 
configurations.  It's been lightly tested on 915GM and 945GM so far, 
additional testing is welcome.  It seems to make a good difference on most 3D 
rendering, but doesn't quite bring it back up to DRI1 levels, so more 
optimization is still needed.  It also won't work on machines with the bit 17 
XOR randomization applied, since the swizzling in that configuration isn't 
supported yet.

-- 
Jesse Barnes, Intel Open Source Technology Center