[Intel-gfx] [PATCH] add fence register management to execbuf

[Eric Anholt]

On Fri, 2009-01-23 at 14:12 -0800, Jesse Barnes wrote:
> Adds code to set up fence registers at execbuf time on pre-965 chips
> as
> necessary.  Also fixes up a few bugs in the pre-965 tile register
> support
> (get_order != ffs).  The number of fences available to the kernel
> defaults
> to the hw limit minus 3 (for legacy X front/back/depth), but a new
> parameter
> allows userspace to override that as needed.
> 
> We should probably be smarter here, and make sure the all the buffers
> are
> covered by fences before hanging the chip, and there may be other
> steps
> required in the fence eviction code (iirc Eric mentioned that some
> additional
> flushing may be required).

Looks pretty good, and thanks for the flushing reminder.  Basically we
need to flush the gpu write domain before waiting for rendering (or
we'll bug!), and we need to clear the read domain flags (or the next
person to come along after setting up their new fence register may get
stale speculated garbage from reads that occurred while the fence reg
wasn't in place).

> -- 
> Jesse Barnes, Intel Open Source Technology Center
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> index 96316fd..41749cd 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1445,21 +1445,27 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
>  	drm_i915_private_t *dev_priv = dev->dev_private;
>  	struct drm_i915_gem_object *obj_priv = obj->driver_private;
>  	int regnum = obj_priv->fence_reg;
> +	int tile_width = 512;
>  	uint32_t val;
>  	uint32_t pitch_val;
>  
>  	if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
>  	    (obj_priv->gtt_offset & (obj->size - 1))) {
> -		WARN(1, "%s: object not 1M or size aligned\n", __func__);
> +		WARN(1, "%s: object 0x%08x not 1M or size (0x%x) aligned\n",
> +		     __func__, obj_priv->gtt_offset, obj->size);
>  		return;
>  	}
>  
>  	if (obj_priv->tiling_mode == I915_TILING_Y && (IS_I945G(dev) ||
>  						       IS_I945GM(dev) ||
>  						       IS_G33(dev)))
> -		pitch_val = (obj_priv->stride / 128) - 1;
> -	else
> -		pitch_val = (obj_priv->stride / 512) - 1;
> +		tile_width = 128;
> +
> +	pitch_val = obj_priv->stride / tile_width;
> +	WARN(pitch_val & (pitch_val - 1),
> +	     "pitch value not a power of two tile widths\n");

SET_TILING ioctl should just reject the tiling request if a bad stride
or a bad tiling type for a given chipset was passed in, so we don't have
to validate and WARN here.

Hmm, actually all the fence management code probably ought to live in
i915_gem_tiling.c.  Something for the next kernel, I guess.

-- 
Eric Anholt
eric at anholt.net                         eric.anholt at intel.com


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