[Intel-gfx] [PATCH] drm/i915: Disable VGA plane reliably

[Jesse Barnes]

On Tue, 21 Jul 2009 11:00:00 +0800
ling.ma at intel.com wrote:

> VGA random hang on recent G45/43 board. From spec, SR01
> bit 5 should be set before VGA plane disable through
> control register, otherwise we might get random crash
> and lockups.
> 
> sync up with 2D driver which fixed freedesktop.org bug #17235
> 
> Signed-off-by: Ma Ling <ling.ma at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   30
> +++++++++++++++++++++++++++++- 1 files changed, 29 insertions(+), 1
> deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c index b6c6a3e..d4e09e6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1273,6 +1273,34 @@ static void igdng_crtc_dpms(struct drm_crtc
> *crtc, int mode) }
>  }
>  
> +static void
> +intel_crtc_disable_vga_plane(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int vgacntrl = I915_READ(VGACNTRL);
> +	uint8_t sr01;
> +
> +	if (vgacntrl & VGA_DISP_DISABLE)
> +		return;
> +	/*
> +	 * Set bit 5 of SR01;
> +	 * Wait 30us;
> +	 */
> +
> +	I915_WRITE8(SRX_INDEX, 1);
> +	sr01 = I915_READ8(SRX_DATA);
> +	I915_WRITE8(SRX_DATA, sr01 | (1 << 5));

What is bit 5?  Can you use a #define here?  Also, shouldn't you be
using the I/O port accessors to get at VGA port space rather than the
MMIO accessors?

> +	udelay(30);
> +	/* disable center mode on 965GM and G4X platform */
> +	if (IS_I965GM(dev) || IS_G4X(dev))
> +		vgacntrl &= ~(3 << 24);
> +	vgacntrl |= VGA_DISP_DISABLE;

3<<24 should probably be a #define or set of #defines too.

Thanks,
-- 
Jesse Barnes, Intel Open Source Technology Center