[Intel-gfx] [PATCH]DRM i915: IGD big FIFO support

[Jesse Barnes]

On Mon, 25 May 2009 10:28:36 +0800
Shaohua Li <shaohua.li at intel.com> wrote:

> On Sat, May 23, 2009 at 03:39:51AM +0800, Eric Anholt wrote:
> > On Mon, 2009-05-18 at 10:44 +0800, Shaohua Li wrote:
> > > +	addr = ioremap(mch_bar, HOSTBAR_SIZE);
> > > +	if (!addr)
> > > +		return -ENOMEM;
> > > +	tmp = *(u32 *)(addr + 0xc00);
> > > +	iounmap(addr);
> > 
> > MCHBAR mapping is tricky.  I think we'll need to use the same code
> > here as i915_gem_tiling.c, and that's changing in 2.6.31 to
> > successfully enable it (safely) more often.
> Makes sense, I fixed the issues you pointed out.
> 
> 
> Big FIFO is a feature to put memory into self-refresh mode when CPU
> enters C3+ state. Gfx has a FIFO to buffer memory access, when the
> watermark of the FIFO is under threshold, Gfx doesn't need access
> memory, so at that time memory can be put into self-refresh mode.
> 
> The watermark calculation is based on CPU C3 state exit latency. If
> watermark is wrong, when CPU enters C3+, display will be broken or
> flicker.
> 
> I had a power measurement about the feature:
> environment: 1920x1400 display, Atom CPU with C4 enabled, system FSB 
> is 667 and memory is DDR2 667. Launch X, and gives system several
> minutes to settle down, then test the power of the whole system in
> idle time: without big fifo, idle power is 19.8w
> with it, idle power is 18.6w
> 
> The patch doesn't enable HPLL off for CxSR. Last time I heard it's
> broken in current IGD chip, if it works, then I'll add it later.

Shaohua, can you take a look at this patch and see if it makes sense to
include in yours?  I think we could probably share the latency tables &
math (haven't checked mine in this patch yet, it's untested on
platforms needing FIFO adjustment) at the very least...

Thanks,
Jesse
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