[Intel-gfx] [PATCH 2/7] Remove fixed MMIO size

[Zhenyu Wang]

On 2009.06.05 11:06:27 +0000, Eric Anholt wrote:
> On Fri, 2009-06-05 at 15:47 +0800, Zhenyu Wang wrote:
> > Use pci resource size instead, which will get the correct MMIO range.
> > New chipset uses obviously larger MMIO range.
> > 
> > Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> > ---
> >  src/common.h      |    1 +
> >  src/i830.h        |    1 +
> >  src/i830_driver.c |   10 ++++++----
> >  3 files changed, 8 insertions(+), 4 deletions(-)
> > 
> > diff --git a/src/common.h b/src/common.h
> > index 69f5604..83ee633 100644
> > --- a/src/common.h
> > +++ b/src/common.h
> > @@ -321,6 +321,7 @@ extern int I810_DEBUG;
> >  #endif
> >  
> >  #define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
> > +#define I810_MEMSIZE(p,n) (p)->regions[(n)].size
> 
> This abstraction existed for libpciaccess vs xf86 pci access, which we
> don't need any more.  Let's not extend that any more, and just use
> pci_dev->regions[].size directly.
> 

Eric, here's the new one which does what you suggested.

commit f4a059aab51b8ea030442dcb040b9443db644f39
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date:   Mon Jun 8 10:22:14 2009 +0800

    Remove fixed MMIO size
    
    Use pci resource size instead, which will get the correct MMIO range.
    New chipset uses obviously larger MMIO range.
    
    Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>

diff --git a/src/i830.h b/src/i830.h
index c0e7dcd..a69f47c 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -415,6 +415,7 @@ typedef struct _I830Rec {
    int Chipset;
    unsigned long LinearAddr;
    unsigned long MMIOAddr;
+   unsigned int MMIOSize;
    IOADDRESS ioBase;
    EntityInfoPtr pEnt;
    struct pci_device *PciInfo;
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 8400872..9d38fba 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -425,7 +425,7 @@ I830MapMMIO(ScrnInfoPtr pScrn)
    device = pI830->PciInfo;
    err = pci_device_map_range (device,
 			       pI830->MMIOAddr,
-			       I810_REG_SIZE,
+			       pI830->MMIOSize,
 			       PCI_DEV_MAP_FLAG_WRITABLE,
 			       (void **) &pI830->MMIOBase);
    if (err) 
@@ -508,7 +508,7 @@ I830UnmapMMIO(ScrnInfoPtr pScrn)
 {
    I830Ptr pI830 = I830PTR(pScrn);
 
-   pci_device_unmap_range (pI830->PciInfo, pI830->MMIOBase, I810_REG_SIZE);
+   pci_device_unmap_range (pI830->PciInfo, pI830->MMIOBase, pI830->MMIOSize);
    pI830->MMIOBase = NULL;
 
    if (IS_I9XX(pI830)) {
@@ -1218,6 +1218,7 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
     if (pI830->pEnt->device->IOBase != 0) {
 	pI830->MMIOAddr = pI830->pEnt->device->IOBase;
 	from = X_CONFIG;
+	pI830->MMIOSize = I810_REG_SIZE;
     } else {
 	pI830->MMIOAddr = I810_MEMBASE (pI830->PciInfo, mmio_bar);
 	if (pI830->MMIOAddr == 0) {
@@ -1226,10 +1227,11 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
 	    PreInitCleanup(pScrn);
 	    return FALSE;
 	}
+	pI830->MMIOSize = pI830->PciInfo->regions[mmio_bar].size;
     }
 
-    xf86DrvMsg(pScrn->scrnIndex, from, "IO registers at addr 0x%lX\n",
-	       (unsigned long)pI830->MMIOAddr);
+    xf86DrvMsg(pScrn->scrnIndex, from, "IO registers at addr 0x%lX size %u\n",
+	       (unsigned long)pI830->MMIOAddr, pI830->MMIOSize);
 
     /* Now figure out mapsize on 8xx chips */
     if (IS_I830(pI830) || IS_845G(pI830)) {

-- 
Open Source Technology Center, Intel ltd.

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