[Intel-gfx] [PATCH V2] drm/i915: assign short type value without a cast

[Ma, Ling]

>-----Original Message-----
>From: intel-gfx-bounces at lists.freedesktop.org 
>[mailto:intel-gfx-bounces at lists.freedesktop.org] On Behalf Of 
>Eric Anholt
>Sent: Friday, June 05, 2009 10:46 PM
>To: Ma, Ling
>Cc: intel-gfx at lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH V2] drm/i915: assign short 
>type value without a cast
>
>On Fri, 2009-05-15 at 16:35 +0800, Ma Ling wrote:
>> If CPU force word address is 2 bytes aligned,
>> unaligned address access will cause system crash.
>
>What Intel CPU is this the case for?
I think it looks like one corner case.
if we  enable alignment checking on x86  by setting bit 18 in cr0
our cpu will generate one bus error if we try using movw instruction to  access unaligned-2byte address.
Thanks
Ma Ling 


>
>> 
>> Signed-off-by: Simon Farnsworth <simon.farnsworth at onelan.com>
>> Signed-off-by: Ma Ling <ling.ma at intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_bios.c |    4 ++--
>>  1 files changed, 2 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c 
>b/drivers/gpu/drm/i915/intel_bios.c
>> index fc28e2b..a463704 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -29,7 +29,7 @@
>>  #include "i915_drm.h"
>>  #include "i915_drv.h"
>>  #include "intel_bios.h"
>> -
>> +#include <linux/unaligned/le_memmove.h>
>>  
>>  static void *
>>  find_section(struct bdb_header *bdb, int section_id)
>> @@ -47,7 +47,7 @@ find_section(struct bdb_header *bdb, int 
>section_id)
>>  	while (index < total) {
>>  		current_id = *(base + index);
>>  		index++;
>> -		current_size = *((u16 *)(base + index));
>> +		current_size = get_unaligned_le16(base + index);
>>  		index += 2;
>>  		if (current_id == section_id)
>>  			return base + index;
>-- 
>Eric Anholt
>eric at anholt.net                         eric.anholt at intel.com
>
>
>