[Intel-gfx] [RFC] execbuf2 support to avoid fence register allocation

[Jesse Barnes]

We'd like to enable texture tiling on pre-965, but for it to be a win
we also need to avoid allocating fence registers for textures.  Even on
pre-965 we have 3D command bits that can help us avoid the use of
fences, and since 915 and before only have 8, it's pretty important to
do so.

I'm still in the process of testing this patchset, but at this point it
no longer crashes in the various config possibilities (new execbuf2 path
on both 965+ and pre-965, old path on both), and seems to
allocate/avoid allocating fence regs in various cases as well.

I'm definitely open to suggestions on how to improve this.  The libdrm
side probably needs the most work; I could probably share more code and
I'm still working on getting the fence register count correct in the
reloc processing code.

Thanks,
-- 
Jesse Barnes, Intel Open Source Technology Center
-------------- next part --------------
A non-text attachment was scrubbed...
Name: i830-execbuf2-support.patch
Type: text/x-patch
Size: 2396 bytes
Desc: not available
URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20090615/a83b581d/attachment.bin>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: mesa-i915-tiling-support-3.patch
Type: text/x-patch
Size: 10570 bytes
Desc: not available
URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20090615/a83b581d/attachment-0001.bin>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: libdrm-execbuf2-4.patch
Type: text/x-patch
Size: 21026 bytes
Desc: not available
URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20090615/a83b581d/attachment-0002.bin>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: i915-execbuf2-7.patch
Type: text/x-patch
Size: 15581 bytes
Desc: not available
URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20090615/a83b581d/attachment-0003.bin>