[Intel-gfx] [PATCH]DRM i915: IGD big FIFO support

[Shaohua Li]

On Fri, Jun 19, 2009 at 03:11:16AM +0800, Jesse Barnes wrote:
> On Thu, 18 Jun 2009 09:12:33 +0800
> Shaohua Li <shaohua.li at intel.com> wrote:
> > > > > I'd like to get both bits of code into 2.6.31 though, so we
> > > > > should get them integrated soon.
> > > > I did some cleanup and try to make it (hopefully) generic. please
> > > > check how to integrate yours.
> > >
> > > Here's the patch I've been testing...  In looking at integrating the
> > > code I found some bugs:
> > >   - intel_crtc->plane wasn't being set properly
> > >   - the FIFO entry calculation was overflowing
> > >   - the CXSR code assumes only one pipe is on (is this safe?)
> > Manual says CxSR can work with one pipe on.
> 
> Right, I should have been clearer: we need to take care to not enable
> CxSR when two pipes are on, right?  I've unified that in the
> update_watermarks code in this patch (before there were two places
> where we'd enable/disable it).
> 
> > >   - watermark update needs to be called at dpms on/off time as well,
> > >     since we could go from a one/two pipe config to one/two/zero at
> > >     that time
> > That's fine. In previous check, it appears dpms on/off might be
> > called in disabled pipe, so my patch bypass cxsr set for disabled
> > pipe. Any reason we shouldn't do this?
> 
> I think that's fine, though running through the code if a pipe is
> disabled should be ok too?
I saw an error running the code in a disabled pipe, but forgot what it is
now.
I'll do some tests and will back to you early next week.

Thanks,
Shaohua