[Intel-gfx] [PATCH] drm/i915: add FIFO watermark support
shaohua.li at intel.com
Thu Jun 25 02:59:13 CEST 2009
On Thu, Jun 25, 2009 at 08:54:13AM +0800, Shaohua Li wrote:
> On Wed, Jun 24, 2009 at 11:59:31PM +0800, Keith Packard wrote:
> > On Wed, 2009-06-24 at 14:00 +0800, Shaohua Li wrote:
> > > updated patch. But I found inconsistent. In the doc at hand, the value of fsb 400
> > > should be 5, instead of 0, what's wrong?
> > Which doc did you find? The one I had didn't have a define for fsb 400,
> > so I guessed...
> then I changed it to 5. The doc is igd's cpu component spec. Also I filted
> the memory freq read except igd, if other chip has the same definition of
> the bits, please remove the filter.
Oops, please ignore this patch. Value 5 is already for FSB 1600, where can we
get the correct definition for all FSB. The doc I has doesn't mention FSB 1600.
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