[Intel-gfx] [PATCH 1/2] drm: Fix EDID detailed timing misc flags decoding

[Keith Packard]

The change from bitfields to masks was done incorrectly for the misc flags
byte.

Signed-off-by: Keith Packard <keithp at keithp.com>
---
 drivers/gpu/drm/drm_edid.c |   19 ++++++++----
 include/drm/drm_edid.h     |   66 ++++++++++++++++++++++++++++++--------------
 2 files changed, 57 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 7d08352..c84b306 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -303,12 +303,16 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
 	if (hactive < 64 || vactive < 64)
 		return NULL;
 
-	if (pt->misc & DRM_EDID_PT_STEREO) {
+	if (DRM_EDID_DETAILED_MISC_HAS_STEREO(pt->misc)) {
 		printk(KERN_WARNING "stereo mode not supported\n");
 		return NULL;
 	}
-	if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
-		printk(KERN_WARNING "integrated sync not supported\n");
+	if (!(pt->misc & DRM_EDID_DETAILED_MISC_DIGITAL_SYNC)) {
+		printk(KERN_WARNING "analog sync not supported\n");
+		return NULL;
+	}
+	if (!(pt->misc & DRM_EDID_DETAILED_MISC_DIGITAL_SYNC_SEPARATE)) {
+		printk(KERN_WARNING "digital composite sync not supported\n");
 		return NULL;
 	}
 
@@ -335,16 +339,17 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
 
 	drm_mode_set_name(mode);
 
-	if (pt->misc & DRM_EDID_PT_INTERLACED)
+	if (pt->misc & DRM_EDID_DETAILED_MISC_INTERLACED)
 		mode->flags |= DRM_MODE_FLAG_INTERLACE;
 
 	if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
-		pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
+		pt->misc |= (DRM_EDID_DETAILED_MISC_DIGITAL_HSYNC_POSITIVE |
+			     DRM_EDID_DETAILED_MISC_DIGITAL_VSYNC_POSITIVE);
 	}
 
-	mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
+	mode->flags |= (pt->misc & DRM_EDID_DETAILED_MISC_DIGITAL_HSYNC_POSITIVE) ?
 		DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
-	mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
+	mode->flags |= (pt->misc & DRM_EDID_DETAILED_MISC_DIGITAL_VSYNC_POSITIVE) ?
 		DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
 
 	mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index c263e4d..8611539 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -47,30 +47,54 @@ struct std_timing {
 	u8 vfreq_aspect;
 } __attribute__((packed));
 
-#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 6)
-#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 5)
-#define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
-#define DRM_EDID_PT_STEREO         (1 << 2)
-#define DRM_EDID_PT_INTERLACED     (1 << 1)
+#define DRM_EDID_DETAILED_MISC_INTERLACED		(1 << 7)
+
+#define DRM_EDID_DETAILED_MISC_STEREO_MASK		((3 << 5) | (1 << 0))
+#define DRM_EDID_DETAILED_MISC_STEREO_NONE_0		((0 << 5) | (0 << 0))
+#define DRM_EDID_DETAILED_MISC_STEREO_NONE_1		((0 << 5) | (1 << 0))
+#define DRM_EDID_DETAILED_MISC_STEREO_FIELD_RIGHT	((1 << 5) | (0 << 0))
+#define DRM_EDID_DETAILED_MISC_STEREO_FIELD_LEFT	((2 << 5) | (0 << 0))
+#define DRM_EDID_DETAILED_MISC_STEREO_2WAY_RIGHT	((1 << 5) | (1 << 0))
+#define DRM_EDID_DETAILED_MISC_STEREO_2WAY_LEFT		((2 << 5) | (1 << 0))
+#define DRM_EDID_DETAILED_MISC_STEREO_4WAY		((3 << 5) | (0 << 0))
+#define DRM_EDID_DETAILED_MISC_STEREO_SIDE_BY_SIDE	((3 << 5) | (1 << 0))
+#define DRM_EDID_DETAILED_MISC_HAS_STEREO(x)		(((x) & (3 << 5)) != 0)
+
+#define DRM_EDID_DETAILED_MISC_DIGITAL_SYNC		(1 << 4)
+/* Analog sync (embedded with signal) */
+#define DRM_EDID_DETAILED_MISC_ANALOG_SYNC_BIPOLAR	(1 << 3)
+#define DRM_EDID_DETAILED_MISC_ANALOG_SYNC_SERRATIONS	(1 << 2)
+#define DRM_EDID_DETAILED_MISC_ANALOG_SYNC_ALL_CHAN	(1 << 1)
+
+/* Digital sync (separate from signal) */
+#define DRM_EDID_DETAILED_MISC_DIGITAL_SYNC_SEPARATE	(1 << 3)
+
+/* Digital composite sync */
+#define DRM_EDID_DETAILED_MISC_DIGITAL_SYNC_SERRATIONS	(1 << 2)
+
+/* Digital separate sync */
+#define DRM_EDID_DETAILED_MISC_DIGITAL_HSYNC_POSITIVE	(1 << 2)
+#define DRM_EDID_DETAILED_MISC_DIGITAL_VSYNC_POSITIVE	(1 << 1)
 
 /* If detailed data is pixel timing */
 struct detailed_pixel_timing {
-	u8 hactive_lo;
-	u8 hblank_lo;
-	u8 hactive_hblank_hi;
-	u8 vactive_lo;
-	u8 vblank_lo;
-	u8 vactive_vblank_hi;
-	u8 hsync_offset_lo;
-	u8 hsync_pulse_width_lo;
-	u8 vsync_offset_pulse_width_lo;
-	u8 hsync_vsync_offset_pulse_width_hi;
-	u8 width_mm_lo;
-	u8 height_mm_lo;
-	u8 width_height_mm_hi;
-	u8 hborder;
-	u8 vborder;
-	u8 misc;
+	/* first two bytes are the clock */
+	u8 hactive_lo;				/* 2 */
+	u8 hblank_lo;				/* 3 */
+	u8 hactive_hblank_hi;			/* 4 */
+	u8 vactive_lo;				/* 5 */
+	u8 vblank_lo;				/* 6 */
+	u8 vactive_vblank_hi;			/* 7 */
+	u8 hsync_offset_lo;			/* 8 */
+	u8 hsync_pulse_width_lo;		/* 9 */
+	u8 vsync_offset_pulse_width_lo;		/* 10 */
+	u8 hsync_vsync_offset_pulse_width_hi;	/* 11 */
+	u8 width_mm_lo;				/* 12 */
+	u8 height_mm_lo;			/* 13 */
+	u8 width_height_mm_hi;			/* 14 */
+	u8 hborder;				/* 15 */
+	u8 vborder;				/* 16 */
+	u8 misc;				/* 17 */
 } __attribute__((packed));
 
 /* If it's not pixel timing, it'll be one of the below */
-- 
1.6.3.1